SBASAI9 December   2025 ADS122S14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Clock Source
      5. 7.3.5  Delta-Sigma Modulator
      6. 7.3.6  Digital Filter
        1. 7.3.6.1 Sinc4 and Sinc4 + Sinc1 Filter
        2. 7.3.6.2 FIR Filter
        3. 7.3.6.3 Digital Filter Latency
        4. 7.3.6.4 Global-Chop Mode
      7. 7.3.7  Excitation Current Sources (IDACs)
      8. 7.3.8  Burn-Out Current Sources (BOCS)
      9. 7.3.9  General Purpose IOs (GPIOs)
        1. 7.3.9.1 FAULT Output
        2. 7.3.9.2 DRDY Output
      10. 7.3.10 System Monitors
        1. 7.3.10.1 Internal Short (Offset Calibration)
        2. 7.3.10.2 Internal Temperature Sensor
        3. 7.3.10.3 External Reference Voltage Readback
        4. 7.3.10.4 Power-Supply Readback
      11. 7.3.11 Monitors and Status Flags
        1. 7.3.11.1 Reset (RESETn flag)
        2. 7.3.11.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.11.3 Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.11.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.11.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.11.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.11.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.11.8 DRDY Indicator (DRDY bit)
        9. 7.3.11.9 Conversion Counter (CONV_COUNT[3:0])
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 Reset by Register Write
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Power-Scalable Conversion Modes
          1. 7.4.2.3.1 Continuous-Conversion Mode
          2. 7.4.2.3.2 Single-shot Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Conversion Data Format
      11. 7.5.11 Register Map CRC
  9. 8 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Interfacing with Multiple Devices
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Device Initialization
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.5.6 Daisy-Chain Operation

In systems using multiple ADCs, the devices can be connected in a daisy-chain string to reduce the number of SPI connections. A daisy-chain connection links together the SPI output (SDO) of one device to the SPI input (SDI) of the next device so the devices in the chain appear as a single logical device to the host controller. There is no special programming required for daisy-chain operation. Apply additional shift clocks to access all devices in the chain. For simplified operation, program the same SPI frame size for each device (for example, when enabling the CRC option of all devices, thus producing a 24-bit (16-bit device), or 32-bit (24-bit device) frame size).

Figure 7-29 shows four devices connected in a daisy-chain configuration. SDI of ADS1x2S14 (1) connects to the host SPI data output, and SDO/DRDY of ADS1x2S14 (4) connects to the host SPI data input. The shift operation is simultaneous for all devices in the chain. After each ADC shifts out the conversion data, the data of SDI appears on SDO/DRDY to drive the SDI of the next device in the chain. The shift operation continues until the last device in the chain is reached. The SPI frame ends when CS is taken high, at which time the data shifted into each device is interpreted. For daisy-chain operation, program the SDO/DRDY pin to data output only mode (SDO_MODE = 0b) and disable continuous-read mode (CONT_READ_EN = 0b).

Connect a pullup resistor on the SDO/DRDY pin of each device to DVDD. When CS is high, SDO/DRDY goes high-Z. The pullup resistors are therefore used to avoid a floating SDI input on the next device in the chain when CS is high.

ADS112S14 ADS122S14 Daisy-Chain Connection Figure 7-29 Daisy-Chain Connection

Figure 7-30 shows the frame structure for four 24-bit devices connected in a daisy-chain with the STATUS header and CRC disabled.

ADS112S14 ADS122S14 Daisy-Chain Data Input Sequence(Four 24-Bit Devices, STATUS Header and CRC Disabled) Figure 7-30 Daisy-Chain Data Input Sequence
(Four 24-Bit Devices, STATUS Header and CRC Disabled)

To input data, the host first shifts in the data intended for the last device in the chain. The number of input bytes for each ADC is sized to match the output frame size. The default frame size is 24 bits (for a 24-bit device), so initially each ADC requires three bytes by prefixing a pad byte in front of the two command bytes. The input data of ADC #4 is shifted in first, followed by the input data of ADC #3, and so forth.

Figure 7-31 shows the detailed input data sequence for the daisy-chain write register operation of Figure 7-29. 48-bit frames for each ADC are shown (24 bits of data, with the STATUS header and CRC enabled). Command operations can be different for each ADC. A register read operation requires a second frame operation to read out the register data.

ADS112S14 ADS122S14 Write Register Data in Daisy-Chain Connection(Four 24-Bit Devices, STATUS Header and CRC Enabled)
A. Optional CRC byte. If CRC is disabled, the frame shortens by one byte.
B. Previous state of SDO/DRDY before SCLK is applied.
C. Optional STATUS header. If STATUS is disabled, the frame shortens by two bytes.
Figure 7-31 Write Register Data in Daisy-Chain Connection
(Four 24-Bit Devices, STATUS Header and CRC Enabled)

Figure 7-32 shows the data sequence to read conversion data from the device connection provided in Figure 7-29. This example illustrates a 32-bit output frame (24 bits of data, with CRC enabled). The conversion data of ADC (4) is shifted out first in the sequence, followed by the data of ADC (3), and so on. The total number of SCLKs required to shift out the data is given by the number of bits per frame × the number of devices in the chain. In this example, 32-bit output frames × four devices result in 128 total clocks.

ADS112S14 ADS122S14 Read Conversion Data in Daisy-Chain Connection(Four 24-Bit Devices, STATUS Header Disabled, CRC Enabled)
A. Optional CRC byte. If CRC is disabled, the frame shortens by one byte.
B. Previous state of SDO/DRDY before SCLK is applied.
Figure 7-32 Read Conversion Data in Daisy-Chain Connection
(Four 24-Bit Devices, STATUS Header Disabled, CRC Enabled)

As shown in Equation 13, the maximum number of devices connected in a daisy-chain configuration is limited by the SCLK signal frequency, the selected data rate, and the number of bits per frame.


Equation 13. Maximum devices in a chain = ⌊fSCLK / (fDATA × bits per frame)⌋

For example, if fSCLK = 10MHz, fDATA = 64kSPS, and 32-bit frames are used, the maximum number of daisy-chain connected devices is the floor of: ⌊10MHz / (64kHz × 32)⌋ = 4.