SBASAI9 December   2025 ADS122S14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Clock Source
      5. 7.3.5  Delta-Sigma Modulator
      6. 7.3.6  Digital Filter
        1. 7.3.6.1 Sinc4 and Sinc4 + Sinc1 Filter
        2. 7.3.6.2 FIR Filter
        3. 7.3.6.3 Digital Filter Latency
        4. 7.3.6.4 Global-Chop Mode
      7. 7.3.7  Excitation Current Sources (IDACs)
      8. 7.3.8  Burn-Out Current Sources (BOCS)
      9. 7.3.9  General Purpose IOs (GPIOs)
        1. 7.3.9.1 FAULT Output
        2. 7.3.9.2 DRDY Output
      10. 7.3.10 System Monitors
        1. 7.3.10.1 Internal Short (Offset Calibration)
        2. 7.3.10.2 Internal Temperature Sensor
        3. 7.3.10.3 External Reference Voltage Readback
        4. 7.3.10.4 Power-Supply Readback
      11. 7.3.11 Monitors and Status Flags
        1. 7.3.11.1 Reset (RESETn flag)
        2. 7.3.11.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.11.3 Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.11.4 SPI CRC Fault (SPI_CRC_FAULTn flag)
        5. 7.3.11.5 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        6. 7.3.11.6 Internal Memory Fault (MEM_FAULTn flag)
        7. 7.3.11.7 Register Write Fault (REG_WRITE_FAULTn flag)
        8. 7.3.11.8 DRDY Indicator (DRDY bit)
        9. 7.3.11.9 Conversion Counter (CONV_COUNT[3:0])
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 Reset by Register Write
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Power-Scalable Conversion Modes
          1. 7.4.2.3.1 Continuous-Conversion Mode
          2. 7.4.2.3.2 Single-shot Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No Operation (Read Conversion Data)
        2. 7.5.4.2 Read Register Command
        3. 7.5.4.3 Write Register Command
      5. 7.5.5  Continuous-Read Mode
        1. 7.5.5.1 Read Registers in Continuous-Read Mode
      6. 7.5.6  Daisy-Chain Operation
      7. 7.5.7  3-Wire SPI Mode
        1. 7.5.7.1 3-Wire SPI Mode Frame Re-Alignment
      8. 7.5.8  Monitoring for New Conversion Data
        1. 7.5.8.1 DRDY Pin or SDO/DRDY Pin Monitoring
        2. 7.5.8.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.8.3 Clock Counting
      9. 7.5.9  DRDY Pin Behavior
      10. 7.5.10 Conversion Data Format
      11. 7.5.11 Register Map CRC
  9. 8 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Interfacing with Multiple Devices
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Device Initialization
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called the oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 6-1 to Table 6-3 summarize the typical device noise performance at TA = 25°C using fCLK = 4.096MHz. The data shown are typical input-referred noise results (en) in units of μVRMS with the analog inputs shorted together. A minimum of 1,000 consecutive conversions or 10 seconds of consecutive conversions (whichever occurs first) are used to measure RMS noise. Because of the statistical nature of noise, repeated noise measurements can yield higher or lower noise results.

Use Equation 1 or Equation 2 to calculate effective resolution from the provided μVRMS numbers, depending on the selected coding scheme.

Equation 1. Binary two's complement coding: Effective Resolution = ln[(2 × VREF / Gain) / en(RMS)] / ln(2)
Equation 2. Unipolar straight binary coding: Effective Resolution = ln[(VREF / Gain) / en(RMS)] / ln(2)

Input-referred noise (en) in units of μVPP can be estimated as en(PP) = 6.6 × en(RMS). Use Equation 3 or Equation 4 to calculate noise-free resolution from the estimated μVPP numbers, depending on the selected coding scheme.

Equation 3. Binary two's complement coding: Noise-free Resolution = ln[(2 × VREF / Gain) / en(PP)] / ln(2)
Equation 4. Unipolar straight binary coding: Noise-free Resolution = ln[(VREF / Gain) / en(PP)] / ln(2)

Input-referred noise performance using shorted inputs does only change insignificantly with the reference voltage. That is, Table 6-1 to Table 6-3 also apply to other reference voltage values.

In global-chop mode, the device averages two measurement of the ADC with the inputs swapped. Global-chop mode significantly reduces the input offset of the device, and reduces noise by a factor of √2.

Noise data is measured using the 24-bit version of the device. For the 16-bit device, clip the noise data at the LSB size.

Table 6-1 Input-referred Noise in μVRMS,
at AVDD = 3.3V, Global-Chop Mode Disabled, Internal 2.5V Reference, Gain = 0.5 to 8
OSR DATA RATE (SPS)(1) GAIN
0.5 1 2 4 5 8
SPEED MODE 0 (fMOD = 32kHz)
1600 20 8.06 3.91 2.20 1.44 1.37 0.99
1280 25 8.44 4.36 2.46 1.51 1.50 1.10
1024 31.25 8.27 4.22 3.32 1.46 1.44 1.07
512 62.5 11.5 5.82 3.27 2.09 2.00 1.47
256 125 16.1 8.18 4.44 2.91 2.91 2.08
128 250 21.6 10.9 6.20 3.80 3.80 2.75
32 1000 33.1 16.5 9.24 5.80 5.80 4.13
16 2000 51.7 26.0 14.1 8.37 8.37 5.81
SPEED MODE 1 (fMOD = 256kHz)
12800 20 2.46 1.32 0.80 0.57 0.57 0.49
10240 25 2.64 1.41 0.82 0.61 0.59 0.54
1024 250 7.34 3.87 2.33 1.69 1.69 1.53
512 500 10.4 5.41 3.23 2.37 2.37 2.15
256 1000 14.4 7.44 4.51 3.31 3.31 2.98
128 2000 19.5 10.2 6.08 4.39 4.39 3.93
32 8000 29.4 15.2 9.10 6.56 6.56 5.76
16 16000 49.4 25.3 14.5 9.78 9.77 8.26
SPEED MODE 2 (fMOD = 512kHz)
25600 20 1.74 0.90 0.51 0.33 0.33 0.28
20480 25 1.85 0.99 0.55 0.35 0.35 0.30
1024 500 7.36 3.75 2.11 1.42 1.40 1.18
512 1000 10.2 5.16 2.93 1.97 1.97 1.65
256 2000 14.3 7.16 4.13 2.73 2.73 2.27
128 4000 19.3 9.82 5.55 3.66 3.65 3.04
32 16000 29.0 14.8 8.34 5.40 5.40 4.45
16 32000 49.4 25.1 13.6 8.31 8.31 6.48
SPEED MODE 3 (fMOD = 1024kHz)
51200 20 1.27 0.67 0.39 0.28 0.28 0.26
40960 25 1.36 0.70 0.41 0.30 0.30 0.27
1024 1000 7.43 3.86 2.27 1.64 1.63 1.55
512 2000 10.4 5.42 3.18 2.29 2.29 2.18
256 4000 14.5 7.47 4.43 3.17 3.17 3.02
128 8000 19.6 10.2 5.93 4.27 4.26 4.03
32 32000 29.5 15.2 8.89 6.31 6.30 5.93
16 64000 50.1 25.6 14.3 9.56 9.56 8.52
(1) Using fCLK = 4.096MHz
Table 6-2 Input-referred Noise in μVRMS,
at AVDD = 3.3V, Global-Chop Mode Disabled, Internal 2.5V Reference, Gain = 10 to 64
OSR DATA RATE (SPS)(1) GAIN
10 16 20 32 50 64
SPEED MODE 0 (fMOD = 32kHz)
1600 20 1.02 0.57 0.57 0.42 0.41 0.33
1280 25 1.07 0.60 0.60 0.43 0.43 0.35
1024 31.25 1.06 0.61 0.58 0.44 0.44 0.34
512 62.5 1.44 0.84 0.79 0.61 0.61 0.48
256 125 2.08 1.15 1.13 0.80 0.80 0.65
128 250 2.75 1.57 1.54 1.11 1.11 0.91
32 1000 4.13 2.36 2.33 1.66 1.66 1.35
16 2000 5.81 3.25 3.25 2.30 2.30 1.80
SPEED MODE 1 (fMOD = 256kHz)
12800 20 0.49 0.31 0.31 0.28 0.28 0.16
10240 25 0.53 0.34 0.34 0.30 0.30 0.17
1024 250 1.51 0.97 0.97 0.87 0.87 0.49
512 500 2.12 1.33 1.31 1.25 1.25 0.68
256 1000 2.98 1.90 1.89 1.72 1.72 0.94
128 2000 3.88 2.42 2.41 2.18 2.16 1.19
32 8000 5.76 3.50 3.50 3.10 3.10 1.59
16 16000 8.26 4.97 4.96 4.37 4.36 2.21
SPEED MODE 2 (fMOD = 512kHz)
25600 20 0.28 0.19 0.19 0.16 0.15 0.10
20480 25 0.30 0.21 0.21 0.17 0.17 0.10
1024 500 1.18 0.82 0.82 0.69 0.69 0.43
512 1000 1.64 1.15 1.15 0.96 0.96 0.59
256 2000 2.27 1.59 1.59 1.37 1.37 0.83
128 4000 3.04 2.10 2.10 1.77 1.74 1.08
32 16000 4.45 3.03 3.03 2.50 2.49 1.55
16 32000 6.48 4.35 4.35 3.53 3.52 2.17
SPEED MODE 3 (fMOD = 1024kHz)
51200 20 0.26 0.17 0.17 0.16 0.16 0.09
40960 25 0.27 0.19 0.19 0.16 0.16 0.10
1024 1000 1.54 1.09 1.09 0.93 0.93 0.58
512 2000 2.17 1.54 1.54 1.31 1.31 0.80
256 4000 2.99 2.13 2.13 1.81 1.81 1.11
128 8000 4.03 2.83 2.83 2.41 2.37 1.48
32 32000 5.92 4.16 4.16 3.47 3.47 2.14
16 64000 8.50 5.92 5.91 4.91 4.91 3.02
(1) Using fCLK = 4.096MHz
Table 6-3 Input-referred Noise in μVRMS,
at AVDD = 3.3V, Global-Chop Mode Disabled, Internal 2.5V Reference, Gain = 100 to 256
OSR DATA RATE (SPS)(1) GAIN
100 128 200 256
SPEED MODE 0 (fMOD = 32kHz)
1600 20 0.327 0.299 0.299 0.268
1280 25 0.347 0.310 0.308 0.305
1024 31.25 0.333 0.301 0.301 0.278
512 62.5 0.474 0.435 0.421 0.387
256 125 0.654 0.589 0.572 0.552
128 250 0.914 0.776 0.776 0.773
32 1000 1.349 1.190 1.187 1.117
16 2000 1.812 1.587 1.574 1.510
SPEED MODE 1 (fMOD = 256kHz)
12800 20 0.146 0.143 0.141 0.134
10240 25 0.164 0.152 0.152 0.141
1024 250 0.482 0.438 0.438 0.426
512 500 0.661 0.635 0.617 0.593
256 1000 0.944 0.900 0.857 0.822
128 2000 1.186 1.086 1.086 1.036
32 8000 1.593 1.441 1.441 1.350
16 16000 2.211 1.987 1.980 1.859
SPEED MODE 2 (fMOD = 512kHz)
25600 20 0.099 0.083 0.083 0.073
20480 25 0.102 0.086 0.084 0.079
1024 500 0.425 0.353 0.353 0.316
512 1000 0.589 0.507 0.505 0.440
256 2000 0.832 0.690 0.690 0.609
128 4000 1.080 0.902 0.896 0.782
32 16000 1.541 1.260 1.251 1.078
16 32000 2.167 1.747 1.746 1.489
SPEED MODE 3 (fMOD = 1024kHz)
51200 20 0.093 0.080 0.079 0.068
40960 25 0.101 0.085 0.083 0.074
1024 1000 0.576 0.484 0.474 0.414
512 2000 0.801 0.666 0.666 0.589
256 4000 1.114 0.929 0.929 0.804
128 8000 1.477 1.221 1.208 1.045
32 32000 2.140 1.742 1.742 1.490
16 64000 3.007 2.436 2.434 2.067
(1) Using fCLK = 4.096MHz