SBASAW5 December   2025 ADS122C14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 I2C Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Clock Source
      5. 7.3.5  Delta-Sigma Modulator
      6. 7.3.6  Digital Filter
        1. 7.3.6.1 Sinc4 and Sinc4 + Sinc1 Filter
        2. 7.3.6.2 FIR Filter
        3. 7.3.6.3 Digital Filter Latency
        4. 7.3.6.4 Global-Chop Mode
      7. 7.3.7  Excitation Current Sources (IDACs)
      8. 7.3.8  Burn-Out Current Sources (BOCS)
      9. 7.3.9  General Purpose IOs (GPIOs)
        1. 7.3.9.1 FAULT Output
        2. 7.3.9.2 DRDY Output
      10. 7.3.10 System Monitors
        1. 7.3.10.1 Internal Short (Offset Calibration)
        2. 7.3.10.2 Internal Temperature Sensor
        3. 7.3.10.3 External Reference Voltage Readback
        4. 7.3.10.4 Power-Supply Readback
      11. 7.3.11 Monitors and Status Flags
        1. 7.3.11.1 Reset (RESETn flag)
        2. 7.3.11.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.11.3 Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.11.4 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        5. 7.3.11.5 Internal Memory Fault (MEM_FAULTn flag)
        6. 7.3.11.6 Register Write Fault (REG_WRITE_FAULTn flag)
        7. 7.3.11.7 DRDY Indicator (DRDY bit)
        8. 7.3.11.8 Conversion Counter (CONV_COUNT[3:0])
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 Reset by Register Write
        3. 7.4.1.3 I2C General Call Reset
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Power-Scalable Conversion Modes
          1. 7.4.2.3.1 Continuous-Conversion Mode
          2. 7.4.2.3.2 Single-shot Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  I2C Interface
      2. 7.5.2  I2C Address
      3. 7.5.3  Serial Clock (SCL) and Serial Data (SDA)
      4. 7.5.4  I2C Bus Speed
      5. 7.5.5  I2C Data Transfer Protocol
      6. 7.5.6  I2C General Call (Software Reset)
      7. 7.5.7  I3C Compatibility
      8. 7.5.8  Commands
        1. 7.5.8.1 RDATA (0000 0000b)
        2. 7.5.8.2 RREG (0100 rrrrb)
        3. 7.5.8.3 WREG (1000 rrrrb)
      9. 7.5.9  STATUS Header
      10. 7.5.10 I2C CRC
      11. 7.5.11 Register Map CRC
      12. 7.5.12 Data Ready (DRDY) Pin
      13. 7.5.13 Monitoring for New Conversion Data
        1. 7.5.13.1 DRDY Pin Monitoring
        2. 7.5.13.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.13.3 Clock Counting
      14. 7.5.14 Conversion Data Format
  9. 8 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Connecting Multiple Devices on the Same I2C Bus
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Device Initialization
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8 Registers

Table 8-1 lists the memory-mapped registers for the Registers registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.

Table 8-1 Register Map
AddressAcronymResetBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
ID Registers - not covered by register map CRC
00hDEVICE_IDXXhDEV_ID[7:0]
01hREVISION_IDXXhREV_ID[7:0]
Status Registers - not covered by register map CRC
02hSTATUS_MSB3EhRESETnAVDD_UVnREF_UVnRESERVEDREG_MAP_CRC_FAULTnMEM_FAULTnREG_WRITE_FAULTnDRDY
03hSTATUS_LSBF0hCONV_COUNT[3:0]GPIO3_DAT_INGPIO2_DAT_INGPIO1_DAT_INGPIO0_DAT_IN
Conversion Control Register - not covered by register map CRC
04hCONVERSION_CTRL00hRESET[5:0]STARTSTOP
Device Configuration Registers - covered by register map CRC
05hDEVICE_CFG00hPWDNSTBY_MODEBOCS[1:0]CLK_SELCONV_MODESPEED_MODE[1:0]
06hDATA_RATE_CFG00hDELAY[3:0]GC_ENFLTR_OSR[2:0]
07hMUX_CFG01hAINP[3:0]AINN[3:0]
08hGAIN_CFG01hSPARESYS_MON[2:0]GAIN[3:0]
09hREFERENCE_CFG00hREF_UV_ENRESERVEDREFP_BUF_ENREFN_BUF_ENRESERVEDREF_VALREF_SEL[1:0]
0AhDIGITAL_CFG00hSPAREREG_MAP_CRC_ENI2C_CRC_ENSTATUS_ENFAULT_PIN_BEHAVIORRESERVEDCODINGRESERVED
0BhGPIO_CFG00hGPIO3_CFG[1:0]GPIO2_CFG[1:0]GPIO1_CFG[1:0]GPIO0_CFG[1:0]
0ChGPIO_DATA_OUTPUT00hGPIO3_SRCGPIO2_SRCRESERVEDGPIO3_DAT_OUTGPIO2_DAT_OUTGPIO1_DAT_OUTGPIO0_DAT_OUT
0DhIDAC_MAG_CFG00hI2MAG[3:0]I1MAG[3:0]
0EhIDAC_MUX_CFG10hIUNITI2MUX[2:0]RESERVEDI1MUX[2:0]
Register Map CRC Value Register
0FhREG_MAP_CRC00hREG_MAP_CRC_VAL[7:0]

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 Registers Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.1 DEVICE_ID Register (Address = 00h) [Reset = XXh]

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Figure 8-1 DEVICE_ID Register
76543210
DEV_ID[7:0]
R-xxxxxxxxb
Table 8-3 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
7:0DEV_ID[7:0]RxxxxxxxxbDevice ID
DEV_ID[7:4] bits are subject to change without notice.
DEV_ID[3:0] bits always read 1111b for the 24-bit device and 1110b for the 16-bit device.

8.2 REVISION_ID Register (Address = 01h) [Reset = XXh]

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Figure 8-2 REVISION_ID Register
76543210
REV_ID[7:0]
R-xxxxxxxxb
Table 8-4 REVISION_ID Register Field Descriptions
BitFieldTypeResetDescription
7:0REV_ID[7:0]RxxxxxxxxbRevision ID
Values are subject to change without notice.

8.3 STATUS_MSB Register (Address = 02h) [Reset = 3Eh]

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Figure 8-3 STATUS_MSB Register
76543210
RESETnAVDD_UVnREF_UVnRESERVEDREG_MAP_CRC_FAULTnMEM_FAULTnREG_WRITE_FAULTnDRDY
R/W-0bR/W-0bR/W-1bR-1bR/W-1bR-1bR-1bR-0b
Table 8-5 STATUS_MSB Register Field Descriptions
BitFieldTypeResetDescription
7RESETnR/W0bReset flag
Indicates a device reset occurred. Write 1b to clear bit to 1b.
  • 0b = Reset occurred
  • 1b = No reset occurred
6AVDD_UVnR/W0bAVDD undervoltage fault flag
Indicates the AVDD supply voltage dropped below the AVDD undervoltage threshold. AVDD_UVn always sets to 0b when entering power-down mode even when the AVDD supply did not drop below the AVDD undervoltage threshold. Write 1b to clear bit to 1b.
  • 0b = Undervoltage fault occurred
  • 1b = No undervoltage fault occurred
5REF_UVnR/W1bReference voltage undervoltage fault flag
Indicates the reference voltage selected by the REF_SEL[1:0] bits dropped below the reference undervoltage threshold. Write 1b to clear bit to 1b. Enable the reference undervoltage monitor using the REF_UV_EN bit.
  • 0b = Undervoltage fault occurred
  • 1b = No undervoltage fault occurred
4RESERVEDR1bReserved
Always reads back 1b.
3REG_MAP_CRC_FAULTnR/W1bRegister map CRC fault flag
Indicates a register map CRC fault occurred. Write 1b to clear bit to 1b. Enable the register map CRC using the REG_MAP_CRC_EN bit.
  • 0b = Register map CRC fault occurred
  • 1b = No register map CRC fault occurred
2MEM_FAULTnR1bMemory map CRC fault flag
Indicates a memory map CRC fault in the internal memory occurred. Perform a power cycle or reset the device when the bit is 0b.
  • 0b = Memory map CRC fault occurred
  • 1b = No memory map CRC fault occurred
1REG_WRITE_FAULTnR1bRegister access fault flag
Indicates a write access to an invalid register address occurred. This flag sets when an invalid register address is written to, and updates at the next register write command. Reading from an invalid register address does not set the flag.
  • 0b = Register access fault occurred
  • 1b = No register access fault occurred
0DRDYR0bData-ready indication bit
Indicates if new data are available for readout. When the transmission of the STATUS header is enabled (STATUS_EN = 1b), the DRDY bit indicates, if the conversion data read within the current I2C frame are new or are repeated data from the last read operation.
  • 0b = Data are not new
  • 1b = Data are new

8.4 STATUS_LSB Register (Address = 03h) [Reset = F0h]

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Figure 8-4 STATUS_LSB Register
76543210
CONV_COUNT[3:0]GPIO3_DAT_INGPIO2_DAT_INGPIO1_DAT_INGPIO0_DAT_IN
R-1111bR-0bR-0bR-0bR-0b
Table 8-6 STATUS_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:4CONV_COUNT[3:0]R1111bConversion counter
The conversion counter increments every time a new conversion completes. After reaching a counter value of Fh, the counter rolls over to 0h with the completion of the next conversion. The counter only resets to Fh (and the conversion data clear) in power-down mode or after a device reset. At the completion of the first conversion after reset or power down, the counter reads 0h.
3GPIO3_DAT_INR0bGPIO3 data
Read back value of GPIO3 when AIN7/GPIO3/DRDY/CLK is configured as digital input, digital output, or DRDY output. Bit reads 0b when the GPIO function is disabled (GPIO3_CFG[1:0] = 00b) or the clock input function is selected (GPIO3_CFG[1:0] = 01b, CLK_SEL = 1b).
  • 0b = Low
  • 1b = High
2GPIO2_DAT_INR0bGPIO2 data
Read back value of GPIO2 when AIN6/GPIO2/FAULT is configured as digital input, digital output, or static FAULT output. Bit reads 0b when the GPIO function is disabled (GPIO2_CFG[1:0] = 00b) or when GPIO2 is configured as FAULT output with heart beat function (GPIO2_CFG[1:0] = 10b or 11b, GPIO2_SRC = 1b, FAULT_PIN_BEHAVIOR = 1b).
  • 0b = Low
  • 1b = High
1GPIO1_DAT_INR0bGPIO1 data
Read back value of GPIO1 when AIN5/REFN/GPIO1 is configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO1_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High
0GPIO0_DAT_INR0bGPIO0 data
Read back value of GPIO0 when AIN4/REFP/GPIO0 is configured as digital input or output. Bit reads 0b when the GPIO function is disabled (GPIO0_CFG[1:0] = 00b).
  • 0b = Low
  • 1b = High

8.5 CONVERSION_CTRL Register (Address = 04h) [Reset = 00h]

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Figure 8-5 CONVERSION_CTRL Register
76543210
RESET[5:0]STARTSTOP
R/W-000000bR/W-0bR/W-0b
Table 8-7 CONVERSION_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7:2RESET[5:0]R/W000000bReset device
Write 010110b to reset the ADC. The START and STOP bits must be set to 0b in the same write operation to reset the ADC. These bits always read 000000b.
1STARTR/W0bStart conversion
Write 1b to start or restart conversions. In single-shot conversion mode, one conversion is started. In continuous conversion mode, conversions are started and continue until stopped by the STOP bit. Writing 1b while a conversion is ongoing restarts the conversion. Writing 1b to both the START and STOP bits at the same time has no effect. The START bit is self-clearing and always reads 0b.
  • 0b = No operation
  • 1b = Start or restart conversion
0STOPR/W0bStop conversion
Write 1b to stop conversions in continuous-conversion mode. Ongoing conversions are allowed to complete. The STOP bit has no effect in single-shot conversion mode. Writing 1b to both the START and STOP bits at the same time has no effect. The STOP bit clears to 0b after the ongoing conversion finishes or when the START bit is set before the ongoing conversion finishes, which aborts the ongoing conversion and restarts a new conversion.
  • 0b = No operation
  • 1b = Stop conversion after the current conversion completes

8.6 DEVICE_CFG Register (Address = 05h) [Reset = 00h]

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Figure 8-6 DEVICE_CFG Register
76543210
PWDNSTBY_MODEBOCS[1:0]CLK_SELCONV_MODESPEED_MODE[1:0]
R/W-0bR/W-0bR/W-00bR/W-0bR/W-0bR/W-00b
Table 8-8 DEVICE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7PWDNR/W0bPower-down mode selection
Powers down all circuitry except for circuitry necessary to retain the user register settings. I2C communication is still possible. In power-down mode, the conversion counter (CONV_COUNT[3:0]) resets to Fh, the conversion data clears, and the START bit is ignored. Setting the PWDN bit to 1b powers the device down immediately; any ongoing conversions are aborted. Any analog inputs configured as GPIO digital outputs transition into a Hi-Z state in power-down mode. To maintain a certain logic level during power down, consider external pullup or pulldown resistors on the respective GPIO pins.
  • 0b = Active mode
  • 1b = Power-down mode
6STBY_MODER/W0bStandby mode selection
This bit enables the auto engagement of the low-power standby mode after conversions are stopped.
  • 0b = Idle mode; device remains fully powered when conversions stop.
  • 1b = Standby mode; when conversions stop, the ADC, PGA, IDACs, BOCS, REF buffers and REF UV monitor power down and the heart beat output signal of the FAULTn pin, if enabled, stops. The FAULTn pin behaves as if configured for static output in standby mode. The internal VREF and AVDD UV monitor stay powered up. The register map CRC and memory map CRC are disabled in standby mode. Standby mode is exited when conversions restart.
5:4BOCS[1:0]R/W00bBurnout current source and sink selection
Enables and selects the value of the burnout current source and sink. Disable the burnout current sources when using global chop mode (GC_EN = 1b).
  • 00b = Disabled
  • 01b = 0.2µA
  • 10b = 1µA
  • 11b = 10µA
3CLK_SELR/W0bClock source selection
Selects the clock source for the device. To change from internal oscillator to external clock, first set GPIO3_CFG = 01b to configure the GPIO3 pin as external clock input, then set CLK_SEL = 1b.
  • 0b = Internal oscillator
  • 1b = External clock
2CONV_MODER/W0bConversion mode selection
Selects the conversion mode for the device.
  • 0b = Continuous-conversion mode
  • 1b = Single-shot conversion mode
1:0SPEED_MODE[1:0]R/W00bSpeed mode selection
Selects the speed mode for the device.
  • 00b = Speed mode 0 (fMOD = 32kHz)
  • 01b = Speed mode 1 (fMOD = 256kHz)
  • 10b = Speed mode 2 (fMOD = 512kHz)
  • 11b = Speed mode 3 (fMOD = 1024kHz)

8.7 DATA_RATE_CFG Register (Address = 06h) [Reset = 00h]

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Figure 8-7 DATA_RATE_CFG Register
76543210
DELAY[3:0]GC_ENFLTR_OSR[2:0]
R/W-0000bR/W-0bR/W-000b
Table 8-9 DATA_RATE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4DELAY[3:0]R/W0000bProgrammable conversion start delay selection
Sets the programmable conversion start delay time for the first conversion after a digital filter reset. This delay time is also used as the delay between conversions when global-chop mode is enabled.
  • 0000b = 0x tMOD
  • 0001b = 1x tMOD
  • 0010b = 2x tMOD
  • 0011b = 4x tMOD
  • 0100b = 8x tMOD
  • 0101b = 16x tMOD
  • 0110b = 32x tMOD
  • 0111b = 64x tMOD
  • 1000b = 128x tMOD
  • 1001b = 256x tMOD
  • 1010b = 512x tMOD
  • 1011b = 1024x tMOD
  • 1100b = 2048x tMOD
  • 1101b = 4096x tMOD
  • 1110b = 8192x tMOD
  • 1111b = 16384x tMOD
3GC_ENR/W0bGlobal-chop mode enable
Enables global-chop mode. When enabled, the device automatically swaps the analog inputs and takes the average of two consecutive conversions to cancel the internal offset voltage.
  • 0b = Disabled
  • 1b = Enabled
2:0FLTR_OSR[2:0]R/W000bFilter OSR selection
Selects the OSR of the digital filter or the output data rate. For settings where an OSR is stated, the output data rate calculates to fDATA = fMOD / OSR. For the 20SPS and 25SPS data rate settings, the digital filter adjusts the OSR automatically based on the selected speed mode. The 20SPS and 25SPS data rates are valid for a nominal clock frequency of fCLK = 4.096MHz. The data rates scale proportional with the clock frequency. At output data rates of 20SPS and 25SPS the digital filter provides 50Hz and 60Hz line-cycle rejection.
  • 000b = OSR = 16 (Sinc4 OSR = 16)
  • 001b = OSR = 32 (Sinc4 OSR = 32)
  • 010b = OSR = 128 (Sinc4 OSR = 32, Sinc1 OSR = 4)
  • 011b = OSR = 256 (Sinc4 OSR = 32, Sinc1 OSR = 8)
  • 100b = OSR = 512 (Sinc4 OSR = 32, Sinc1 OSR = 16)
  • 101b = OSR = 1024 (Sinc4 OSR = 32, Sinc1 OSR =32)
  • 110b = fDATA = 25SPS (independent of speed mode)
  • 111b = fDATA = 20SPS (independent of speed mode)

8.8 MUX_CFG Register (Address = 07h) [Reset = 01h]

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Figure 8-8 MUX_CFG Register
76543210
AINP[3:0]AINN[3:0]
R/W-0000bR/W-0001b
Table 8-10 MUX_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4AINP[3:0]R/W0000bPositive multiplexer input selection
Selects the positive analog input for the ADC. Analog inputs AIN4 and AIN5 can still be used as analog inputs, even when the inputs are configured as REFP and REFN inputs, respectively. When an analog input is configured as GPIO, the analog input can still be selected by the Mux and used to measure back the voltage on the GPIO pin.
  • 0000b = AIN0
  • 0001b = AIN1
  • 0010b = AIN2
  • 0011b = AIN3
  • 0100b = AIN4
  • 0101b = AIN5
  • 0110b = AIN6
  • 0111b = AIN7
  • 1000b = GND
  • 1001b = GND
  • 1010b = GND
  • 1011b = GND
  • 1100b = GND
  • 1101b = GND
  • 1110b = GND
  • 1111b = GND
3:0AINN[3:0]R/W0001bNegative multiplexer input selection
Selects the negative analog input for the ADC. Analog inputs AIN4 and AIN5 can still be used as analog inputs, even when the inputs are configured as REFP and REFN inputs, respectively. When an analog input is configured as GPIO, the analog input can still be selected by the Mux and used to measure back the voltage on the GPIO pin.
  • 0000b = AIN0
  • 0001b = AIN1
  • 0010b = AIN2
  • 0011b = AIN3
  • 0100b = AIN4
  • 0101b = AIN5
  • 0110b = AIN6
  • 0111b = AIN7
  • 1000b = GND
  • 1001b = GND
  • 1010b = GND
  • 1011b = GND
  • 1100b = GND
  • 1101b = GND
  • 1110b = GND
  • 1111b = GND

8.9 GAIN_CFG Register (Address = 08h) [Reset = 01h]

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Figure 8-9 GAIN_CFG Register
76543210
SPARESYS_MON[2:0]GAIN[3:0]
R/W-0bR/W-000bR/W-0001b
Table 8-11 GAIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7SPARER/W0bSpare bit
Bit setting has no effect. Provided as R/W bit as a means to check the register map CRC.
6:4SYS_MON[2:0]R/W000bSystem monitor selection
Selects one of the system monitors as the inputs for the PGA. The AINP[3:0] and AINN[3:0] bits have no effect when one of the system monitors is selected. The analog inputs are disconnected from the PGA when a system monitor is selected. The internal reference with the value set in the REF_VAL bit is automatically selected for settings 010b to 101b. Select an appropriate PGA gain setting for the respective measurement.
  • 000b = Disabled
  • 001b = Internal short of differential PGA inputs to (AVDD / 2)
  • 010b = Internal temperature sensor
  • 011b = External (VREFP – VREFN) / 8
  • 100b = AVDD / 8
  • 101b = DVDD / 8
  • 110b = Do not use
  • 111b = Do not use
3:0GAIN[3:0]R/W0001bPGA gain selection
Selects the gain of the PGA.
  • 0000b = 0.5
  • 0001b = 1
  • 0010b = 2
  • 0011b = 4
  • 0100b = 5
  • 0101b = 8
  • 0110b = 10
  • 0111b = 16
  • 1000b = 20
  • 1001b = 32
  • 1010b = 50
  • 1011b = 64
  • 1100b = 100
  • 1101b = 128
  • 1110b = 200
  • 1111b = 256

8.10 REFERENCE_CFG Register (Address = 09h) [Reset = 00h]

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Figure 8-10 REFERENCE_CFG Register
76543210
REF_UV_ENRESERVEDREFP_BUF_ENREFN_BUF_ENRESERVEDREF_VALREF_SEL[1:0]
R/W-0bR-0bR/W-0bR/W-0bR-0bR/W-0bR/W-00b
Table 8-12 REFERENCE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7REF_UV_ENR/W0bReference voltage monitor enable
Enables the voltage reference monitor to detect when the selected voltage reference, as selected by the REF_SEL[1:0] bits, drops below the reference undervoltage threshold.
  • 0b = Disabled
  • 1b = Enabled
6RESERVEDR0bReserved
Always reads back 0b.
5REFP_BUF_ENR/W0bPositive reference buffer enable
Enables the positive reference buffer. Disable the positive reference buffer when the internal reference or the analog supply is selected as the reference source using the REF_SEL[1:0] bit field.
  • 0b = Disabled
  • 1b = Enabled
4REFN_BUF_ENR/W0bNegative reference buffer enable
Enables the negative reference buffer. Disable the negative reference buffer when the internal reference or the analog supply is selected as the reference source using the REF_SEL[1:0] bit field.
  • 0b = Disabled
  • 1b = Enabled
3RESERVEDR0bReserved
Always reads back 0b.
2REF_VALR/W0bInternal reference voltage value selection
Selects the voltage of the internal reference. The internal voltage reference is always enabled.
  • 0b = 1.25V
  • 1b = 2.5V
1:0REF_SEL[1:0]R/W00bReference voltage selection
Selects the reference voltage for the ADC. Set GPIO0_CFG[1:0] = 00b and GPIO1_CFG[1:0] = 00b when the external voltage reference is selected.
  • 00b = Internal voltage reference
  • 01b = External voltage reference
  • 10b = AVDD
  • 11b = AVDD

8.11 DIGITAL_CFG Register (Address = 0Ah) [Reset = 00h]

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Figure 8-11 DIGITAL_CFG Register
76543210
SPAREREG_MAP_CRC_ENI2C_CRC_ENSTATUS_ENFAULT_PIN_BEHAVIORRESERVEDCODINGRESERVED
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR-0bR/W-0bR-0b
Table 8-13 DIGITAL_CFG Register Field Descriptions
BitFieldTypeResetDescription
7SPARER/W0bSpare bit
Bit setting has no effect. Provided as R/W bit as a means to check the register map CRC.
6REG_MAP_CRC_ENR/W0bRegister map CRC enable
Enables the register map CRC for register addresses 05h to 0Eh.
  • 0b = Disabled
  • 1b = Enabled
5I2C_CRC_ENR/W0bI2C CRC enable
Enables the I2C output CRC for register and conversion data reads.
  • 0b = Disabled
  • 1b = Enabled
4STATUS_ENR/W0bSTATUS header output enable
Enables the STATUS header (STATUS_MSB + STATUS_LSB registers) transmission as the first two bytes of every conversion data read.
  • 0b = Disabled
  • 1b = Enabled
3FAULT_PIN_BEHAVIORR/W0bFAULT pin behavior selection
Selects the behavior of the FAULT pin, when GPIO2 is configured as FAULT output (GPIO2_CFG = 10b or 11b, GPIO2_SRC = 1b).
  • 0b = Static. Output is low when a fault occurred, otherwise output is high.
  • 1b = Heart beat. Output is low when a fault occurred, otherwise output is a 50% duty-cycle signal with a frequency of fMOD / 256.
2RESERVEDR0bReserved
Always reads back 0b.
1CODINGR/W0bConversion data coding selection
Selects the coding of the conversion data.
  • 0b = Binary two's complement
  • 1b = Unipolar straight binary
0RESERVEDR0bReserved
Always reads back 0b.

8.12 GPIO_CFG Register (Address = 0Bh) [Reset = 00h]

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Figure 8-12 GPIO_CFG Register
76543210
GPIO3_CFG[1:0]GPIO2_CFG[1:0]GPIO1_CFG[1:0]GPIO0_CFG[1:0]
R/W-00bR/W-00bR/W-00bR/W-00b
Table 8-14 GPIO_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:6GPIO3_CFG[1:0]R/W00bGPIO3 configuration
Configures the GPIO3 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input (CLK_SEL = 0b) or external clock input (CLK_SEL = 1b)
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
5:4GPIO2_CFG[1:0]R/W00bGPIO2 configuration
Configures the GPIO2 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
3:2GPIO1_CFG[1:0]R/W00bGPIO1 configuration
Configures the GPIO1 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)
1:0GPIO0_CFG[1:0]R/W00bGPIO0 configuration
Configures the GPIO0 pin behavior.
  • 00b = Disabled (High-Z)
  • 01b = Digital input
  • 10b = Push-pull digital output (with readback)
  • 11b = Open-drain digital output (with readback)

8.13 GPIO_DATA_OUTPUT Register (Address = 0Ch) [Reset = 00h]

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Figure 8-13 GPIO_DATA_OUTPUT Register
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GPIO3_SRCGPIO2_SRCRESERVEDGPIO3_DAT_OUTGPIO2_DAT_OUTGPIO1_DAT_OUTGPIO0_DAT_OUT
R/W-0bR/W-0bR-00bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-15 GPIO_DATA_OUTPUT Register Field Descriptions
BitFieldTypeResetDescription
7GPIO3_SRCR/W0b GPIO3 data source selection
Selects the data source of the GPIO3 pin when GPIO3 is configured as digital output.
  • 0b = GPIO3_DAT_OUT bit
  • 1b = DRDY
6GPIO2_SRCR/W0b GPIO2 data source selection
Selects the data source of the GPIO2 pin when GPIO2 is configured as digital output. The FAULT pin is low when any of the AVDD_UVn, REF_UVn, REG_MAP_CRC_FAULTn, or MEM_FAULTn status bits are 0b.
  • 0b = GPIO2_DAT_OUT bit
  • 1b = FAULT
5:4RESERVEDR00bReserved
Always reads back 00b.
3GPIO3_DAT_OUTR/W0bGPIO3 data
Write value of GPIO3 when configured as digital output. Bit setting has no effect when GPIO3 is configured as digital input or as digital output with DRDY as the data source.
  • 0b = Low
  • 1b = High
2GPIO2_DAT_OUTR/W0bGPIO2 data
Write value of GPIO2 when configured as digital output. Bit setting has no effect when GPIO2 is configured as digital input or as digital output with FAULT as the data source.
  • 0b = Low
  • 1b = High
1GPIO1_DAT_OUTR/W0bGPIO1 data
Write value of GPIO1 when configured as digital output. Bit setting has no effect when GPIO1 is configured as digital input.
  • 0b = Low
  • 1b = High
0GPIO0_DAT_OUTR/W0bGPIO0 data
Write value of GPIO0 when configured as digital output. Bit setting has no effect when GPIO0 is configured as digital input.
  • 0b = Low
  • 1b = High

8.14 IDAC_MAG_CFG Register (Address = 0Dh) [Reset = 00h]

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Figure 8-14 IDAC_MAG_CFG Register
76543210
I2MAG[3:0]I1MAG[3:0]
R/W-0000bR/W-0000b
Table 8-16 IDAC_MAG_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4I2MAG[3:0]R/W0000bIDAC2 magnitude selection
Selects the value of the excitation current source, IDAC2.
  • 0000b = Disabled
  • 0001b = 1x IUNIT
  • 0010b = 10x IUNIT
  • 0011b = 20x IUNIT
  • 0100b = 30x IUNIT
  • 0101b = 40x IUNIT
  • 0110b = 50x IUNIT
  • 0111b = 60x IUNIT
  • 1000b = 70x IUNIT
  • 1001b = 80x IUNIT
  • 1010b = 90x IUNIT
  • 1011b = 100x IUNIT
  • 1100b = 100x IUNIT
  • 1101b = 100x IUNIT
  • 1110b = 100x IUNIT
  • 1111b = 100x IUNIT
3:0I1MAG[3:0]R/W0000bIDAC1 magnitude selection
Selects the value of the excitation current source, IDAC1.
  • 0000b = Disabled
  • 0001b = 1x IUNIT
  • 0010b = 10x IUNIT
  • 0011b = 20x IUNIT
  • 0100b = 30x IUNIT
  • 0101b = 40x IUNIT
  • 0110b = 50x IUNIT
  • 0111b = 60x IUNIT
  • 1000b = 70x IUNIT
  • 1001b = 80x IUNIT
  • 1010b = 90x IUNIT
  • 1011b = 100x IUNIT
  • 1100b = 100x IUNIT
  • 1101b = 100x IUNIT
  • 1110b = 100x IUNIT
  • 1111b = 100x IUNIT

8.15 IDAC_MUX_CFG Register (Address = 0Eh) [Reset = 10h]

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Figure 8-15 IDAC_MUX_CFG Register
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IUNITI2MUX[2:0]RESERVEDI1MUX[2:0]
R/W-0bR/W-001bR-0bR/W-000b
Table 8-17 IDAC_MUX_CFG Register Field Descriptions
BitFieldTypeResetDescription
7IUNITR/W0bIDAC unit current selection
Selects the unit current for the excitation current sources, IDAC1 and IDAC2.
  • 0b = 1µA
  • 1b = 10µA
6:4I2MUX[2:0]R/W001bIDAC2 output pin selection
Selects the output pin for IDAC2. IDAC1 and IDAC2 can be routed to the same pin if needed. An analog input that is used as an IDAC2 output, can still be used as an analog or reference input.
  • 000b = AIN0
  • 001b = AIN1
  • 010b = AIN2
  • 011b = AIN3
  • 100b = AIN4
  • 101b = AIN5
  • 110b = AIN6
  • 111b = AIN7
3RESERVEDR0bReserved
Always reads back 0b.
2:0I1MUX[2:0]R/W000bIDAC1 output pin selection
Selects the output pin for IDAC1. IDAC1 and IDAC2 can be routed to the same pin if needed. An analog input that is used as an IDAC1 output, can still be used as an analog or reference input.
  • 000b = AIN0
  • 001b = AIN1
  • 010b = AIN2
  • 011b = AIN3
  • 100b = AIN4
  • 101b = AIN5
  • 110b = AIN6
  • 111b = AIN7

8.16 REG_MAP_CRC Register (Address = 0Fh) [Reset = 00h]

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Figure 8-16 REG_MAP_CRC Register
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REG_MAP_CRC_VAL[7:0]
R/W-00000000b
Table 8-18 REG_MAP_CRC Register Field Descriptions
BitFieldTypeResetDescription
7:0REG_MAP_CRC_VAL[7:0]R/W00000000bRegister map CRC value
The register map CRC value is the user-computed CRC value of registers 05h to 0Eh. The CRC value written to this register is compared to an internal CRC calculation. If the values do not match, the REG_MAP_CRC_FAULTn bit in the STATUS_MSB register is set. Enable the register map CRC using the REG_MAP_CRC_EN bit.