SBASAW5 December   2025 ADS122C14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 I2C Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs and Multiplexer
      2. 7.3.2  Programmable Gain Amplifier (PGA)
      3. 7.3.3  Voltage Reference
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
        3. 7.3.3.3 Reference Buffers
      4. 7.3.4  Clock Source
      5. 7.3.5  Delta-Sigma Modulator
      6. 7.3.6  Digital Filter
        1. 7.3.6.1 Sinc4 and Sinc4 + Sinc1 Filter
        2. 7.3.6.2 FIR Filter
        3. 7.3.6.3 Digital Filter Latency
        4. 7.3.6.4 Global-Chop Mode
      7. 7.3.7  Excitation Current Sources (IDACs)
      8. 7.3.8  Burn-Out Current Sources (BOCS)
      9. 7.3.9  General Purpose IOs (GPIOs)
        1. 7.3.9.1 FAULT Output
        2. 7.3.9.2 DRDY Output
      10. 7.3.10 System Monitors
        1. 7.3.10.1 Internal Short (Offset Calibration)
        2. 7.3.10.2 Internal Temperature Sensor
        3. 7.3.10.3 External Reference Voltage Readback
        4. 7.3.10.4 Power-Supply Readback
      11. 7.3.11 Monitors and Status Flags
        1. 7.3.11.1 Reset (RESETn flag)
        2. 7.3.11.2 AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.11.3 Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.11.4 Register Map CRC Fault (REG_MAP_CRC_FAULTn flag)
        5. 7.3.11.5 Internal Memory Fault (MEM_FAULTn flag)
        6. 7.3.11.6 Register Write Fault (REG_WRITE_FAULTn flag)
        7. 7.3.11.7 DRDY Indicator (DRDY bit)
        8. 7.3.11.8 Conversion Counter (CONV_COUNT[3:0])
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-up and Reset
        1. 7.4.1.1 Power-On Reset (POR)
        2. 7.4.1.2 Reset by Register Write
        3. 7.4.1.3 I2C General Call Reset
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Idle and Standby Mode
        2. 7.4.2.2 Power-Down Mode
        3. 7.4.2.3 Power-Scalable Conversion Modes
          1. 7.4.2.3.1 Continuous-Conversion Mode
          2. 7.4.2.3.2 Single-shot Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  I2C Interface
      2. 7.5.2  I2C Address
      3. 7.5.3  Serial Clock (SCL) and Serial Data (SDA)
      4. 7.5.4  I2C Bus Speed
      5. 7.5.5  I2C Data Transfer Protocol
      6. 7.5.6  I2C General Call (Software Reset)
      7. 7.5.7  I3C Compatibility
      8. 7.5.8  Commands
        1. 7.5.8.1 RDATA (0000 0000b)
        2. 7.5.8.2 RREG (0100 rrrrb)
        3. 7.5.8.3 WREG (1000 rrrrb)
      9. 7.5.9  STATUS Header
      10. 7.5.10 I2C CRC
      11. 7.5.11 Register Map CRC
      12. 7.5.12 Data Ready (DRDY) Pin
      13. 7.5.13 Monitoring for New Conversion Data
        1. 7.5.13.1 DRDY Pin Monitoring
        2. 7.5.13.2 Reading DRDY Bit and Conversion Counter
        3. 7.5.13.3 Clock Counting
      14. 7.5.14 Conversion Data Format
  9. 8 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Connecting Multiple Devices on the Same I2C Bus
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Device Initialization
    2. 9.2 Typical Applications
      1. 9.2.1 Software-Configurable RTD Measurement Input
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Performance Plots
        4. 9.2.1.4 Design Variant – 3-Wire RTD Measurement With Automatic Lead-Wire Compensation Using Two IDACs
      2. 9.2.2 Thermocouple Measurement With Cold-Junction Compensation Using a 2-wire RTD
      3. 9.2.3 Resistive Bridge Sensor Measurement With Temperature Compensation
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.5.10 I2C CRC

The ADS1x2C14 can output an 8-bit cyclic redundancy check (CRC) code when sending conversion data or register data to the controller to detect transmission errors. Use the I2C_CRC_EN bit to enable the I2C CRC. The devices append the CRC byte after the conversion data or register data, respectively, as shown in Figure 7-19, Figure 7-20, and Figure 7-22.

The number of bytes used to calculate the CRC code depends on the amount of data bytes transmitted in the frame. Table 7-11 shows the data included in the CRC calculation.

Table 7-11 Data Covered by CRC
ACTION DEVICE RESOLUTION STATUS HEADER ENABLED DATA COVERD BY CRC
Conversion data read 16 bit No 16 bits of conversion data + 8 bits of zero padding
Yes 16 bits STATUS header + 16 bits of conversion data + 8 bits of zero padding
24 bit No 24 bits of conversion data
Yes 16 bits STATUS header + 24 bits of conversion data
Register data read 16 or 24 bit N/A 8 bits of register data

The CRC code calculation is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the variable length argument with the CRC polynomial. The CRC is based on the CRC-8-ATM (HEC) polynomial: X8 + X2 + X1 + 1. The nine coefficients of the polynomial are: 100000111. The CRC calculation is initialized to all 1s to detect errors in the event that SDI and SDO/DRDY are either stuck high or low.

Figure 7-24 shows a visual representation of the CRC calculation. The following procedure calculates the CRC value:

  • Preload the 8-bit shift register, which has XOR blocks located at positions that correspond to the CRC polynomial (07h), with the seed value of FFh.
  • Shift in all data bits starting with the most-significant bit (MSB) and re-compute the shift-register value after each bit.
  • The resulting shift-register value after all data bits have been shifted in is the computed CRC value.

The example C code available for download here includes a potential CRC implementation.

ADS112C14 ADS122C14 Visual Representation of CRC Calculation Figure 7-24 Visual Representation of CRC Calculation

Register data written to the devices are not CRC protected. To detect transmission errors when writing to the devices, read back the register data after a register has been written.