SBASAX4 June   2026 ADS9316 , ADS9317

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics 
    6. 5.6  Electrical Characteristics: AVDD = 5V
    7. 5.7  Electrical Characteristics: AVDD = 3.3V
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Reference
        1. 6.3.2.1 Internal Reference
          1. 6.3.2.1.1 Selectable Internal Reference with 5V AVDD
        2. 6.3.2.2 External Reference
        3. 6.3.2.3 External Reference With External Reference Buffer
      3. 6.3.3 Burst Sample Operation
      4. 6.3.4 ADC Transfer Function
      5. 6.3.5 Programmable Data Averaging Filter
        1. 6.3.5.1 Simple Average
          1. 6.3.5.1.1 Simple Average with Noncontinuous CONVST
        2. 6.3.5.2 Moving Average
      6. 6.3.6 Channel Averaging
      7. 6.3.7 Common-Mode Voltage Output
      8. 6.3.8 ADC Output Data Randomizer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Low-Latency Mode
      4. 6.4.4 CS-CONVST Short Mode
      5. 6.4.5 Register Read Mode
      6. 6.4.6 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1  Data Interface
      2. 6.5.2  Data Frame Width
      3. 6.5.3  SPI Modes
      4. 6.5.4  CONVST Inversion
      5. 6.5.5  SCLK Echo Mode
      6. 6.5.6  Daisy-Chain Mode
      7. 6.5.7  SPI Frame Length for Register Operations
      8. 6.5.8  Register Map Lock
      9. 6.5.9  Register Write
      10. 6.5.10 Register Read
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Analog 1VPP Sine-Cosine Encoder Interface
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

6.4.4 CS-CONVST Short Mode

In CS-CONVST short mode, tie CS and CONVST together externally. As illustrated in Figure 5-4, the ADS931x digitizes sample N on the falling edge of CONVST. Data corresponding to sample N − 1 are launched on the digital interface on the falling edge of CS. CS-CONVST short mode is supported by default and creates a 5ns internal delay between the falling edge of CONVST and CS. The internal delay between CONVST and CS is disabled by writing 1b to CSZ_CONVST_DELAY_DIS in address 0x13.