SBASAX4 June   2026 ADS9316 , ADS9317

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics 
    6. 5.6  Electrical Characteristics: AVDD = 5V
    7. 5.7  Electrical Characteristics: AVDD = 3.3V
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Reference
        1. 6.3.2.1 Internal Reference
          1. 6.3.2.1.1 Selectable Internal Reference with 5V AVDD
        2. 6.3.2.2 External Reference
        3. 6.3.2.3 External Reference With External Reference Buffer
      3. 6.3.3 Burst Sample Operation
      4. 6.3.4 ADC Transfer Function
      5. 6.3.5 Programmable Data Averaging Filter
        1. 6.3.5.1 Simple Average
          1. 6.3.5.1.1 Simple Average with Noncontinuous CONVST
        2. 6.3.5.2 Moving Average
      6. 6.3.6 Channel Averaging
      7. 6.3.7 Common-Mode Voltage Output
      8. 6.3.8 ADC Output Data Randomizer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Low-Latency Mode
      4. 6.4.4 CS-CONVST Short Mode
      5. 6.4.5 Register Read Mode
      6. 6.4.6 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1  Data Interface
      2. 6.5.2  Data Frame Width
      3. 6.5.3  SPI Modes
      4. 6.5.4  CONVST Inversion
      5. 6.5.5  SCLK Echo Mode
      6. 6.5.6  Daisy-Chain Mode
      7. 6.5.7  SPI Frame Length for Register Operations
      8. 6.5.8  Register Map Lock
      9. 6.5.9  Register Write
      10. 6.5.10 Register Read
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Analog 1VPP Sine-Cosine Encoder Interface
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

5.8 Timing Requirements

at AVDD = 3V to 5.5V, VDD_1V8 = 1.75V to 1.85V, IOVDD = 1.75V to 3.3V, internal reference, and maximum throughput (unless otherwise noted); CL = 10pF; minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
MIN MAX UNIT
CONVERSION CYCLE
fCYCLE Sampling frequency ADS9317 5 MHz
ADS9316 3
tCYCLE ADC cycle-time period 1/fCYCLE s
fCLK Maximum SCLK frequency 80 MHz
tCLK Minimum SCLK time period 12.5 ns
tACQ Acquisition time ADS9317 70 ns
ADS9316 133.33
tPH_CV CONVST high time 10 ns
tPL_CV CONVST low time 10 ns
SPI INTERFACE TIMINGS
thi_CSZ Pulse duration: CS high 5 ns
tPH_CK SCLK high time 0.40 0.60 tCLK
tPL_CK SCLK low time 0.40 0.60 tCLK
td_CSCK Setup time: CS falling to the first SCLK rising edge 10 ns
tsu_CKDI Setup time: SDI data valid to the corresponding SCLK rising edge 3 ns
tht_CKDI Hold time: SCLK rising edge to corresponding data valid on SDI 1 ns
tht_CVCS(1) Hold time: CONVST falling edge to CS falling edge 0 ns
tht_CKCS Hold time: last SCLK falling edge to CS rising 10 ns
tLOW_LAT(2) Hold time: time after tCONV to CS falling edge in low latency mode 30 ns
(1) Internally there is a 5ns delay enabled by default between CONVST falling edge and CS falling edge.
(2) For more details, see the LL_DELAY register field description in register bank 1.