SBASAX4 June   2026 ADS9316 , ADS9317

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics 
    6. 5.6  Electrical Characteristics: AVDD = 5V
    7. 5.7  Electrical Characteristics: AVDD = 3.3V
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Timing Diagrams
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Reference
        1. 6.3.2.1 Internal Reference
          1. 6.3.2.1.1 Selectable Internal Reference with 5V AVDD
        2. 6.3.2.2 External Reference
        3. 6.3.2.3 External Reference With External Reference Buffer
      3. 6.3.3 Burst Sample Operation
      4. 6.3.4 ADC Transfer Function
      5. 6.3.5 Programmable Data Averaging Filter
        1. 6.3.5.1 Simple Average
          1. 6.3.5.1.1 Simple Average with Noncontinuous CONVST
        2. 6.3.5.2 Moving Average
      6. 6.3.6 Channel Averaging
      7. 6.3.7 Common-Mode Voltage Output
      8. 6.3.8 ADC Output Data Randomizer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Normal Operation
      3. 6.4.3 Low-Latency Mode
      4. 6.4.4 CS-CONVST Short Mode
      5. 6.4.5 Register Read Mode
      6. 6.4.6 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1  Data Interface
      2. 6.5.2  Data Frame Width
      3. 6.5.3  SPI Modes
      4. 6.5.4  CONVST Inversion
      5. 6.5.5  SCLK Echo Mode
      6. 6.5.6  Daisy-Chain Mode
      7. 6.5.7  SPI Frame Length for Register Operations
      8. 6.5.8  Register Map Lock
      9. 6.5.9  Register Write
      10. 6.5.10 Register Read
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Analog 1VPP Sine-Cosine Encoder Interface
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

7.2 Register Bank 1

Table 7-5 lists the memory-mapped registers for the Register Bank 1 registers. All register offset addresses not listed in Table 7-5 should be considered as reserved locations and the register contents should not be modified.

Table 7-5 Register Map Bank 1
AddressAcronymBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x08Register 08hRESERVED
RESERVEDPDN_CH[1:0]RESERVEDPDN_CTL
0x09Register 09hRESERVEDLATENCY_MODERESERVED
RESERVEDNUM_DATA_LANES[2:0]RESERVEDSPI_MODE[1:0]SCLK_ECHO
0x0ARegister 0AhRESERVEDSDO_PD_OVERRIDE
RESERVEDDIG_DELAY_ENDRIVE_STRENGTH[2:0]
0x0BRegister 0BhRESERVEDDIG_DELAY_D3[2:0]DIG_DELAY_D2[2:0]
DIG_DELAY_D2[2:0]DIG_DELAY_D1[2:0]DIG_DELAY_D0[2:0]
0x0CRegister 0ChRESERVEDPD_REF[1:0]
RESERVEDCLK_PWR[2:0]RESERVED
0x0DRegister 0DhXOR_EN[4:0]RESERVEDCH_AVERAGEDATA_FORMAT
SAVG_MODE[3:0]MAVG_MODE[1:0]AVG_SYNCSAVG_EN
0x0FRegister 0FhRESERVEDTEST_PATT_2_LSB[3:0]TEST_PATT_1_LSB[3:0]
TEST_PATT_1_LSB[3:0]TEST_RAMP_RSTRESERVEDTEST_PATT_MODE[1:0]TEST_PATT_EN_CHBTEST_PATT_EN_CHA
0x10Register 10hTEST_PATT_1_MSB[15:0]
TEST_PATT_1_MSB[15:0]
0x11Register 11hTEST_PATT_2_MSB[15:0]
TEST_PATT_2_MSB[15:0]
0x13Register 13hCSZ_CONVST_INTERNAL_SHORTRESERVED
CSZ_CONVST_DELAY_DISRESERVEDPD_REFBUFRESERVED
0x14Register 14hRESERVEDCONVST_INVERT
RESERVEDINT_BUFFERINT_REF_MODE[1:0]
0x17Register 17hRESERVED
RESERVEDLL_DELAY[2:0]RESERVED
0x39Register 39hRESERVEDDIS_VCMOUTVCMOUT_SEL[2:0]RESERVED
RESERVED
0x48Register 48hLFN_COMP[15:0]
LFN_COMP[15:0]

Complex bit access types are encoded to fit into small table cells. Table 7-6 shows the codes that are used for access types in this section.

Table 7-6 Register Bank 1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.2.1 Register 08h (Address = 0x08) [Reset = 0x0000]

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Figure 7-3 Register 08h
15141312111098
RESERVED
R/W-000000000000b
76543210
RESERVEDPDN_CH[1:0]RESERVEDPDN_CTL
R/W-000000000000bR/W-00bR/W-0bR/W-0b
Table 7-7 Register 08h Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR/W000000000000bReserved. Do not change from the default reset value.
3:2PDN_CH[1:0]R/W00bPower-down control for the analog input channels.
  • 00b = Normal device operation.
  • 01b = Channel A powered down.
  • 10b = Channel B powered down.
  • 11b = Both channels powered down.
1RESERVEDR/W0bReserved. Do not change from the default reset value.
0PDN_CTLR/W0bFull device power-down control
  • 0b = Normal device operation.
  • 1b = Full device power-down control.

7.2.2 Register 09h (Address = 0x09) [Reset = 0x0000]

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Figure 7-4 Register 09h
15141312111098
RESERVEDLATENCY_MODERESERVED
R/W-00000bR/W-0bR/W-000b
76543210
RESERVEDNUM_DATA_LANES[2:0]RESERVEDSPI_MODE[1:0]SCLK_ECHO
R/W-000bR/W-000bR/W-0bR/W-00bR/W-0b
Table 7-8 Register 09h Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR/W00000bReserved. Do not change from the default reset value.
10LATENCY_MODER/W0bControl to select latency mode.
  • 0b = Data corresponding to sample N - 1 is launched on CS falling edge during sample N frame.
  • 1b = Low latency mode is active. Data corresponding to sample N is launched on CS falling edge during sample N frame. CS high until tCONV (max) + tLOW_LAT.
9:7RESERVEDR/W000bReserved. Do not change from the default reset value.
6:4NUM_DATA_LANES[2:0]R/W000bControl to select the number of lanes used for the serial data interface.
  • 000b = ADC A data output on D[3:2] and ADC B data output on D[1:0].
  • 101b = ADC A data output on D3 and ADC B data output on D1. D2 and D0 are HI-Z.
  • 110b = ADC A and ADC B data output on D3. D[2:0] are HI-Z.
3RESERVEDR/W0bReserved. Do not change from the default reset value.
2:1SPI_MODE[1:0]R/W00bControl to select the SPI mode.
  • 00b = Mode 0.
  • 01b = Mode 1.
  • 10b = Mode 2.
  • 11b = Mode 3.
0SCLK_ECHOR/W0bControl to feed-through SCLK (Pin 17) on D0 (Pin 16) .
  • 0b = D0 outputs data as per the data interface configuration.
  • 1b = D0 feeds-through SCLK.

7.2.3 Register 0Ah (Address = 0x0A) [Reset = 0x0000]

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Figure 7-5 Register 0Ah
15141312111098
RESERVEDSDO_PD_OVERRIDE
R/W-0000000bR/W-0b
76543210
RESERVEDDIG_DELAY_ENDRIVE_STRENGTH[2:0]
R/W-0000bR/W-0bR/W-000b
Table 7-9 Register 0Ah Field Descriptions
BitFieldTypeResetDescription
15:9RESERVEDR/W0000000bReserved. Do not change from the default reset value.
8SDO_PD_OVERRIDER/W0bControl to override power down of serial data output lines when in 1-lane and 2-lane mode.
  • 0b = Unused data output lines are powered down in 1-lane and 2-lane mode.
  • 1b = All data output lines are powered up in 1-lane and 2-lane mode to support SCLK echo mode.
7:4RESERVEDR/W0000bReserved. Do not change from the default reset value.
3DIG_DELAY_ENR/W0bControl for digital delay on the output buffer path.
  • 0b = Normal device operation.
  • 1b = Digital delay on the output buffer path is enabled. The magnitude is controlled by DIG_DELAY_Dx fields in address 0Bh.
2:0DRIVE_STRENGTH[2:0]R/W000bControl to configure the drive strength of the digital output buffer.
  • 000b = Normal device operation.
  • 101b = 0.5x drive strength.
  • 110b = 2x drive strength.
  • 111b = 1.5x drive strength.

7.2.4 Register 0Bh (Address = 0x0B) [Reset = 0x0000]

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Figure 7-6 Register 0Bh
15141312111098
RESERVEDDIG_DELAY_D3[2:0]DIG_DELAY_D2[2:0]
R/W-0000bR/W-000bR/W-000b
76543210
DIG_DELAY_D2[2:0]DIG_DELAY_D1[2:0]DIG_DELAY_D0[2:0]
R/W-000bR/W-000bR/W-000b
Table 7-10 Register 0Bh Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0000bReserved. Do not change from the default reset value.
11:9DIG_DELAY_D3[2:0]R/W000bProgrammable digital delay on D3.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.
8:6DIG_DELAY_D2[2:0]R/W000bProgrammable digital delay on D2.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.
5:3DIG_DELAY_D1[2:0]R/W000bProgrammable digital delay on D1.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.
2:0DIG_DELAY_D0[2:0]R/W000bProgrammable digital delay on D0.
  • 000b = 0ns delay.
  • 001b = 1ns delay.
  • 010b = 2ns delay.
  • 011b = 3ns delay.
  • 100b = 4ns delay.
  • 101b = 5ns delay.

7.2.5 Register 0Ch (Address = 0x0C) [Reset = 0x0000]

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Figure 7-7 Register 0Ch
15141312111098
RESERVEDPD_REF[1:0]
R/W-000000bR/W-00b
76543210
RESERVEDCLK_PWR[2:0]RESERVED
R/W-0bR/W-000bR/W-0000b
Table 7-11 Register 0Ch Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved. Do not change from the default reset value.
9:8PD_REF[1:0]R/W00bADC reference voltage source selection.
  • 00b = Normal device operation. Internal reference is active.
  • 10b = Internal reference is active.
  • 11b = Internal reference is inactive. Force an external reference via REFIO (pin 9).
7RESERVEDR/W0bReserved. Do not change from the default reset value.
6:4CLK_PWR[2:0]R/W000bControl to select the power supply domain for the input clock.
  • 000b = IOVDD domain.
  • 101b = VDD_1V8 domain.
3:0RESERVEDR/W0000bReserved. Do not change from the default reset value.

7.2.6 Register 0Dh (Address = 0x0D) [Reset = 0x0000]

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Figure 7-8 Register 0Dh
15141312111098
XOR_EN[4:0]RESERVEDCH_AVERAGEDATA_FORMAT
R/W-00000bR/W-0bR/W-0bR/W-0b
76543210
SAVG_MODE[3:0]MAVG_MODE[1:0]AVG_SYNCSAVG_EN
R/W-0000bR/W-00bR/W-0bR/W-0b
Table 7-12 Register 0Dh Field Descriptions
BitFieldTypeResetDescription
15:11XOR_EN[4:0]R/W00000bControl to enable XOR operation on the ADC conversion result.
  • 00000b = XOR operation is inactive.
  • 01111b = Bit-wise XOR operation on the ADC conversion result is active.
10RESERVEDR/W0bReserved. Do not change from the default reset value.
9CH_AVERAGER/W0bControl to enable averaging of the two ADC channels.
  • 0b = Normal device operation.
  • 1b = Data output is the average of channel A and channel B.
8DATA_FORMATR/W0bControl to select the data format for the ADC conversion result.
  • 0b = Two's complement format.
  • 1b = Straight binary format.
7:4SAVG_MODE[3:0]R/W0000bControl for the number of samples to be averaged in simple averaging mode.
  • 0000b = 2 samples averaged.
  • 0001b = 4 samples averaged.
  • 0010b = 8 samples averaged.
  • 0011b = 16 samples averaged.
  • 0100b = 32 samples averaged.
  • 0101b = 64 samples averaged.
  • 0110b = 128 samples averaged.
3:2MAVG_MODE[1:0]R/W00bControl for the number of samples to be averaged in moving average mode.
  • 00b = Moving average is inactive.
  • 01b = 2 moving samples averaged.
  • 10b = 4 moving samples averaged.
  • 11b = 8 moving samples averaged.
1AVG_SYNCR/W0bSynchronization control for the internal averaging filter in simple averaging mode.
Write 1b to trigger when averaging starts from the subsequent cycle. This should be used only during the initialization of simple averaging.
0SAVG_ENR/W0bControl to enable simple averaging. Select the number of samples to be averaged in SAVG_MODE.
  • 0b = Simple averaging is inactive.
  • 1b = Simple averaging is active.

7.2.7 Register 0Fh (Address = 0x0F) [Reset = 0x0000]

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Figure 7-9 Register 0Fh
15141312111098
RESERVEDTEST_PATT_2_LSB[3:0]TEST_PATT_1_LSB[3:0]
R/W-0bR/W-0000bR/W-0000b
76543210
TEST_PATT_1_LSB[3:0]TEST_RAMP_RSTRESERVEDTEST_PATT_MODE[1:0]TEST_PATT_EN_CHBTEST_PATT_EN_CHA
R/W-0000bR/W-0bR/W-00bR/W-00bR/W-0bR/W-0b
Table 7-13 Register 0Fh Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0bReserved. Do not change from the default reset value.
14:11TEST_PATT_2_LSB[3:0]R/W0000bLSB 4-bit test pattern corresponding to ADC B.
10:7TEST_PATT_1_LSB[3:0]R/W0000bLSB 4-bit test pattern corresponding to ADC A.
6TEST_RAMP_RSTR/W0bControl to reset the ramp pattern to start from 0.
Toggle this register bit to reset the ramp pattern when TEST_PATT_MODE is set to ramp pattern.
5:4RESERVEDR/W00bReserved. Do not change from the default reset value.
3:2TEST_PATT_MODE[1:0]R/W00bType of test pattern at the data interface.
  • 00b = ADC outputs constant pattern defined in TEST_PATT_1_MSB in address 0x10 and TEST_PATT_1_LSB in address 0x0F for ADC A. Test pattern for ADC B is defined in TEST_PATT_2_MSB in address 0x11 and TEST_PATT_2_LSB in address 0x0F.
  • 01b = Ramp pattern.
  • 10b = Alternate pattern between AAAA and 5555 toggled at each readout.
1TEST_PATT_EN_CHBR/W0bControl to enable digital test pattern for ADC B.
  • 0b = ADC conversion result is launched on the data interface.
  • 1b = Digital test pattern is launched on the data interface.
0TEST_PATT_EN_CHAR/W0bControl to enable digital test pattern for ADC A.
  • 0b = ADC conversion result is launched on the data interface.
  • 1b = Digital test pattern is launched on the data interface.

7.2.8 Register 10h (Address = 0x10) [Reset = 0x0000]

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Figure 7-10 Register 10h
15141312111098
TEST_PATT_1_MSB[15:0]
R/W-0000000000000000b
76543210
TEST_PATT_1_MSB[15:0]
R/W-0000000000000000b
Table 7-14 Register 10h Field Descriptions
BitFieldTypeResetDescription
15:0TEST_PATT_1_MSB[15:0]R/W0000000000000000bMSB 16-bit test pattern corresponding to ADC A.

7.2.9 Register 11h (Address = 0x11) [Reset = 0x0000]

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Figure 7-11 Register 11h
15141312111098
TEST_PATT_2_MSB[15:0]
R/W-0000000000000000b
76543210
TEST_PATT_2_MSB[15:0]
R/W-0000000000000000b
Table 7-15 Register 11h Field Descriptions
BitFieldTypeResetDescription
15:0TEST_PATT_2_MSB[15:0]R/W0000000000000000bMSB 16-bit test pattern corresponding to ADC B.

7.2.10 Register 13h (Address = 0x13) [Reset = 0x0000]

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Figure 7-12 Register 13h
15141312111098
CSZ_CONVST_INTERNAL_SHORTRESERVED
R/W-0bR/W-0000000b
76543210
CSZ_CONVST_DELAY_DISRESERVEDPD_REFBUFRESERVED
R/W-0bR/W-000bR/W-0bR/W-000b
Table 7-16 Register 13h Field Descriptions
BitFieldTypeResetDescription
15CSZ_CONVST_INTERNAL_SHORTR/W0bControl to internally short CONVST and CS.
  • 0b = Normal device operation.
  • 1b = CONVST and CS are shorted internally. Connect CONVST/CS signal to CONVST pin.
14:8RESERVEDR/W0000000bReserved. Do not change from the default reset value.
7CSZ_CONVST_DELAY_DISR/W0bControl to disable internal 5ns delay between CONVST and CS falling edges.
  • 0b = Normal device operation.
  • 1b = Disable internal 5ns delay between CONVST and CS. td_CSCK reduces to 12ns and tht_CVCS increases to 5ns.
6:4RESERVEDR/W000bReserved. Do not change from the default reset value.
3PD_REFBUFR/W0bControl to power down the internal reference buffer.
  • 0b = Internal reference buffer is active.
  • 1b = Internal reference buffer is inactive. Use an external reference buffer and connect the external reference to the REFIO and REF_CAP pins.
2:0RESERVEDR/W000bReserved. Do not change from the default reset value.

7.2.11 Register 14h (Address = 0x14) [Reset = 0x0000]

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Figure 7-13 Register 14h
15141312111098
RESERVEDCONVST_INVERT
R/W-0000000bR/W-0b
76543210
RESERVEDINT_BUFFERINT_REF_MODE[1:0]
R/W-00000bR/W-0bR/W-00b
Table 7-17 Register 14h Field Descriptions
BitFieldTypeResetDescription
15:9RESERVEDR/W0000000bReserved. Do not change from the default reset value.
8CONVST_INVERTR/W0bControl to invert CONVST such that the sampling operation occurs on the rising edge of CONVST.
  • 0b = Normal device operation. Sampling occurs on the falling edge of CONVST.
  • 1b = CONVST is inverted. Sampling occurs on the rising edge of CONVST.
7:3RESERVEDR/W00000bReserved. Do not change from the default reset value.
2INT_BUFFERR/W0bControl to disable internal input buffer and reduce AVDD current. The input buffer helps improve the acquisition accuracy when the ADC is driven using weaker drive networks. It is not recommended to disable the input buffer unless the ADC driver network is sufficient to drive the input with the input buffer disabled. In ADS9316, the internal buffer is inactive by default. For signals with input frequency greater than 500kHz, the input buffer should be disabled.
  • 0b = Internal buffer is active (ADS9317). Internal buffer is inactive (ADS9316).
  • 1b = Internal buffer is inactive (ADS9317). Internal buffer is active (ADS9316).
1:0INT_REF_MODE[1:0]R/W00bControl to select internal reference voltage when AVDD is 5V.
  • 00b = 4.096V internal reference.
  • 01b = 2.5V internal reference.
  • 11b = 3.3V internal reference.

7.2.12 Register 17h (Address = 0x17) [Reset = 0x0000]

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Figure 7-14 Register 17h
15141312111098
RESERVED
R/W-00000000000b
76543210
RESERVEDLL_DELAY[2:0]RESERVED
R/W-00000000000bR/W-000bR/W-00b
Table 7-18 Register 17h Field Descriptions
BitFieldTypeResetDescription
15:5RESERVEDR/W00000000000bReserved. Do not change from the default reset value.
4:2LL_DELAY[2:0]R/W000bControl to select the delay after tCONV when low latency data is ready for readout.
  • 000b = Normal device operation. The delay between end of conversion and low latency data is ready for readout is 30ns.
  • 110b = The delay between end of conversion and low latency data is ready for readout is 15ns.
1:0RESERVEDR/W00bReserved. Do not change from the default reset value.

7.2.13 Register 39h (Address = 0x39) [Reset = 0x0000]

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Figure 7-15 Register 39h
15141312111098
RESERVEDDIS_VCMOUTVCMOUT_SEL[2:0]RESERVED
R/W-0bR/W-0bR/W-000bR/W-00000000000b
76543210
RESERVED
R/W-00000000000b
Table 7-19 Register 39h Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0bReserved. Do not change from the default reset value.
14DIS_VCMOUTR/W0bControl to disable VCMOUT.
  • 0b = VCMOUT is active.
  • 1b = VCMOUT is inactive.
13:11VCMOUT_SEL[2:0]R/W000bControl to select the VCMOUT voltage.
  • 000b = 2.23V.
  • 001b = 2.17V.
  • 010b = 2.11V.
  • 011b = 2.04V.
  • 100b = 2.49V.
  • 101b = 2.43V.
  • 110b = 2.36V.
  • 111b = 2.29V.
10:0RESERVEDR/W00000000000bReserved. Do not change from the default reset value.

7.2.14 Register 48h (Address = 0x48) [Reset = 0x40E0]

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Figure 7-16 Register 48h
15141312111098
LFN_COMP[15:0]
R/W-0100000011100000b
76543210
LFN_COMP[15:0]
R/W-0100000011100000b
Table 7-20 Register 48h Field Descriptions
BitFieldTypeResetDescription
15:0LFN_COMP[15:0]R/W0100000011100000bControl to enable low frequency noise compensation.
  • 0100000011100000b = Normal device operation. Low frequency noise compensation is inactive.
  • 0100000010100001b = Low frequency noise compensation is active.