SBOK097B April   2025  – June 2025 TMP9R01-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Sample Identification
  6. 3 Irradiation Facility and Setup
  7. 4 Die Micro-section
  8. 5 Test Set-Up
  9. 6 SEL Results
    1. 6.1 TMP9R01-SEP SEL Data
  10. 7 SET Results
    1. 7.1 Summary of SET Results
      1. 7.1.1 Local Temperature Reads
        1. 7.1.1.1 Analog Alert Captures
    2. 7.2 Cross Section Events and Event Rate Calculations
  11. 8 Detailed Results Per Run
    1. 8.1 Detailed Run Raw Data
  12. 9 Summary
  13. 10Glossary
  14. 11Revision History

4 Die Micro-section

The TMP9R01-SEP is fabricated in the TI Linear BiCMOS 180-nm process with a back-end-of-line (BEOL) stack consisting of 3 levels of standard thickness aluminum metal on a 0.6μm pitch. The total stack height from the surface of the passivation to the silicon surface is 3.825μm based on nominal layer thickness as shown in Figure 4-1. Accounting for energy loss through the 1mil thick Aramica beam port window, the 40mm air gap, and the BEOL stack over the TMP9R01-SEP, the effective LET (LETEFF) at the surface of the silicon substrate, the depth, and the ion range was determined with the SEUSS 2020 Software (provided by the Texas A&M Cyclotron Institute and based on the latest SRIM-2013 models). The stack was modeled as a homogeneous layer of silicon dioxide (valid since SiO2 and aluminum density are similar). At MSU, the LETEFF reported is the surface-level LET.

Generalized Cross-Section of the LBC8 Technology BEOL Stack on the TMP9R01-SEP Figure 4-1 Generalized Cross-Section of the LBC8 Technology BEOL Stack on the TMP9R01-SEP