SBOS258E November   2002  – April 2025 OPA698

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics VS = ±5V
    6. 6.6 Electrical Characteristics VS = 5V
    7. 6.7 Typical Characteristics: VS = ±5V
    8. 6.8 Typical Characteristics: VS = 5V
  8. 7 Detailed Description
    1. 7.1 Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Limiters
      2. 8.1.2  Output Drive
      3. 8.1.3  Thermal Considerations
      4. 8.1.4  Capacitive Loads
      5. 8.1.5  Frequency Response Compensation
      6. 8.1.6  Pulse Settling Time
      7. 8.1.7  Distortion
      8. 8.1.8  Noise Performance
      9. 8.1.9  DC Accuracy and Offset Control
      10. 8.1.10 Input and ESD Protection
    2. 8.2 Typical Applications
      1. 8.2.1  Wideband Voltage-Limiting Operation
      2. 8.2.2  Single-Supply, Noninverting Amplifier
      3. 8.2.3  Wideband Inverting Operation
      4. 8.2.4  Limited Output, ADC Input Driver
        1. 8.2.4.1 Limited-Output, Differential ADC Input Driver
        2. 8.2.4.2 Precision Half-Wave Rectifier
      5. 8.2.5  High-Speed Full-Wave Rectifier
        1. 8.2.5.1 High-Speed Full-Wave Rectifier #1
        2. 8.2.5.2 High-Speed Full-Wave Rectifier #2
      6. 8.2.6  Soft-Clipping (Compression) Circuit
      7. 8.2.7  Very High-Speed Schmitt Trigger
      8. 8.2.8  Unity-Gain Buffer
      9. 8.2.9  DC Restorer
      10. 8.2.10 Video Sync Stripper
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Demonstration Fixture
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics VS = ±5V

at TA ≅ 25°C, RF = 402Ω, RL = 500Ω, G = 2V/V, VH = –VL = 2V, and input and output referenced to midsupply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE 
SSBW Small-signal bandwidth G = 1V/V, VO = 0.2VPP, RF = 25Ω 650 MHz
G = 2V/V, VO = 0.2VPP 215
G = –1V/V, VO = 0.2VPP 215
GBP Gain bandwidth product G ≥ 5V/V 300 MHz
Bandwidth for 0.1dB gain flatness VO = 0.2VPP 30 MHz
Peaking at a gain of 1V/V RF = 25Ω, VO = 0.2VPP 1.5 dB
Large-signal bandwidth VO = 4VPP   VH = – VL = 2.5V 160 MHz
Slew rate 4V step,  VH = – VL = 2.5V 1800 V/µs
Rise-and-fall time VO = 0.2V step 1.4 ns
Settling time 0.05%, VO = 2V step 25 ns
2nd-order harmonic distortion f = 5MHz, VO = 2VPP, RL = 500Ω –94 dBc
3rd-order harmonic distortion f = 5MHz, VO = 2VPP, RL = 500Ω –85 dBc
Input voltage noise f ≥ 1MHz 4 nV/√Hz
Input current noise f ≥ 1MHz 1.5 pA/√Hz
DC PERFORMANCE(1)
AOL Open-loop voltage gain VO = ±0.5V 56 80 dB
TA = –40°C to +85°C 52
VOS Input offset voltage ±2 ±5 mV
TA = –40°C to +85°C ±8
Average offset voltage drift TA = –40°C to +85°C ±20 µV/°C
Input bias current(1) +0.2 ±10 µA
TA = –40°C to +85°C ±12
Average bias current drift TA = –40°C to +85°C ±20 nA/°C
Input offset current ±0.1
±2

 µA
TA = –40°C to +85°C
±3
Average offset current drift TA = –40°C to +85°C ±10 nA/°C
INPUT
CMIR Common-mode input voltage(2)
±3.2

 ±3.3 V
TA = –40°C to +85°C
±3.1
CMRR Common-mode rejection ratio VCM = ±0.5V 55 82 dB
TA = –40°C to +85°C 52
Input impedance Differential mode  1 || 0.3 MΩ || pF
Common-mode 33 || 1.4
OUTPUT
Voltage output swing RL = 500Ω, VH = –VL = 4.3V ±3.9 ±4.0
 		 V
TA = –40°C to +85°C ±3.8
Current output Sourcing, VO = 0V 90 190  mA
TA = –40°C to +85°C 80
Sinking, VO = 0V  –90 –190
TA = –40°C to +85°C –80
Closed-loop output impedance G = 1V/V, RF = 25Ω, f < 100kHz 0.01 Ω
OUTPUT VOLTAGE LIMITER
Output voltage limited range Pins 5 and 8 ±3.8 V
TA = –40°C to +85°C
Default limit voltage, upper Limiter pins open +3.3
+3.5

 V
TA = –40°C to +85°C +3.1
Default limit voltage, lower Limiter pins open –3.3 –3.5 V

TA = –40°C to +85°C
 		 –3.1
Minimum limiter separation (VH –VL) 400 400 mV
TA = –40°C to +85°C 400
Maximum limit voltage ±4.3 V
TA = –40°C to +85°C ±4.3
Limiter input bias current magnitude(3) VO = 0V 40 50 60 µA
TA = –40°C to +85°C 36 65

Limiter input bias average drift
 		 TA = –40°C to +85°C 35
nA/℃
Limiter input impedance 10 || 0.85 MΩ || pF
Limiter feedthrough(4) f = 5MHz –68  dB
Limiter offset VIN = ±2V,
VO – VH) or (VO – VL)		 ±5 ±30 mV
TA = –40°C to +85°C ±40
Op amp input bias current shift VIN = ±2V, linear to limited output 0.15 µA
 
Limiter small-signal bandwidth 2VDC + 20mVPP 700 MHz
Limiter slew rate(5) 2 × overdrive, VH or VL 175 V/µs
Limiter overshoot 2 × overdrive, VIN = VCM to VCM ±2V step 250 mV
Recovery time 2 × overdrive VIN = ±2V to 0V step 1 ns
Linearity guardband(6) f = 5MHz, VO = 2VPP f = 5MHz, VO = 2VPP 30 mV
POWER SUPPLY
Quiescent current VS = ±5V  13.8 15.5 17.3 mA
TA = –40°C to +85°C 13.4 17.7
PSRR Power-supply rejection ratio Input-referred 68 90 dB
TA = –40°C to +85°C 66
(1) Current is considered positive out of node.
(2) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
(3) IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Figure 7-8 and Figure 7-15.
(4) Limiter feedthrough is the ratio of the output magnitude to the sine wave added to VH (or VL) when VIN = 0V.
(5) VH slew rate conditions are: VIN = 2V, G = 2V/V, VL = –2V, VH = step between 2V and 0V. VL slew rate conditions are similar.
(6) Linearity guardband is defined for an output sinusoid (f = 5MHz, VO = 0VDC ±1VPP) centered between the limiter levels (VH and VL). Linearity guardband is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB.