10 Revision History
Changes from Revision D (December 2008) to Revision E (April 2025)
- Updated Features, Applications, and
Description sections and with die redesign specifications; for
updated specifications, see the Specifications sectionGo
- Updated the numbering format for tables, figures, and
cross-references throughout the documentGo
- Added Pin Configuration and Functions
Go
- Changed the supply voltage specification from ±6.5V to 13V in Absolute Maximum Ratings
Go
- Updated the table note in Absolute Maximum Ratings to add clarificationGo
- Added Supply turn-on and turn-off rate and Continuous input current to Absolute Maximum Ratings
Go
- Deleted soldering flow specification from Absolute maximum specifications
Go
- Deleted machine model (MM) specification from ESD Ratings
Go
- Added Recommended Operating Conditions
Go
- Deleted minimum and overtemperature specifications in both Electrical Characteristics AC Performance
Go
- Updated test conditions to both Electrical Characteristics for added clarityGo
- Updated table format for both Electrical Characteristics
Go
- Deleted TA = 0°C to +70°C specifications from all Electrical Characteristics
Go
- Deleted Test Level column from all Electrical Characteristics
Go
- Changed SSBW at G = 1V/V from 450MHz to 650MHzGo
- Added TA = 25°C to the default test conditions to both Electrical Characteristics.Go
- Updated AC Performance section with improved typical small signal bandwidth, slew rate, voltage noise, current noise, and distortion values in both Electrical Characteristics
Go
- Changed Gain bandwidth product from 250MHz to 300MHzGo
- Changed typical Peaking at a gain of 1V/V from 5dB to 1.5dBGo
- Changed typical Slew rate from 1100V/µs to 1800V/µsGo
- Changed Rise and fall time at VO = 0.2V Step from 1.6ns to 1.4nsGo
- Changed Settling time from 8ns to 25nsGo
- Changed typical 2nd-order harmonic distortion at RL = 500Ω from –74dBc to –94dBcGo
- Deleted Differential gain and Differential phase specificationsGo
- Changed typical 3rd-order harmonic distortion at RL = 500Ω from –87dBc to –85dBcGo
- Changed typical Open-loop voltage gain from 63dB to 80dBGo
- Changed typical Input bias current from 3µA to ±0.2µA and Input offset current from ±0.3µA to ±0.1µAGo
- Changed typical Common-mode rejection ratio from 61dB to 82dBGo
- Changed Input impedance Differential-mode from 0.32 || 1MΩ || pF to 1 || 0.3MΩ || pFGo
- Changed the typical Input impedance common-mode from 3.5 || 1MΩ || pF to 33 || 1.4MΩ || pFGo
- Changed Current output sourcing and sinking from 120mA and –120mA to +190mA and –190mAGo
- Changed maximum Limiter input bias current magnitude, TA = –40°C to +85°C from 64µA to 65µAGo
- Changed the typical Limiter input impedance from 3.4 || 1 MΩ || pF to 10 || 0.85 MΩ || pFGo
- Changed typical Limiter feedthrough from –68dB to –95dBGo
- Changed typical Limiter offset ±5mV from ±10mVGo
- Changed Op amp input bias current shift from 3µA to 0.15µAGo
- Changed Limiter small signal bandwidth from 600MHz to 700MHzGo
- Changed Limiter slew rate from 125V/µs to 175V/µs Go
- Changed maximum and minimum Quiescent current from 15.9mA to 17.3mA and 15.2mA to 13.8mAGo
- Changed minimum and maximum Quiescent current, TA = –40°C to +85°C from 16.6mA to 17.7mA and 14.6mA to 13.4mAGo
- Changed typical Power-supply rejection ratio from 75dB to 90dBGo
- Moved Thermal Characteristics to Thermal Information table and Recommended Operating Conditions tableGo
- Changed SSBW at G = 1V/V from 375MHz to 550MHzGo
- Changed Gain bandwidth product from 230MHz to 300MHzGo
- Changed typical Bandwidth for 0.1dB gain flatness typical value from 30MHz to 26MHzGo
- Changed typical Peaking at a gain of 1V/V from 7dB to 2.5dBGo
- Changed Rise and fall time at VO = 0.2V step from 1.9ns to 1.4nsGo
- Changed Settling time from 12ns to 28nsGo
- Changed typical 2nd-order harmonic distortion at RL = 500Ω from 69dBc to –95dBcGo
- Changed typical 3rd-order harmonic distortion at RL = 500Ω from 73dBc to –81dBcGo
- Changed the typical Input voltage noise from 5.7nV/√Hz to 4nV/√HzGo
- Changed the typical Input current noise from 2.3pA/√Hz to 1.4pA/√HzGo
- Changed typical Open-loop voltage gain from 60dB to 77dBGo
- Changed typical Input bias current from ±3μA to ±0.5μA and Input offset current from ±0.4μA to ±0.1μAGo
- Changed typical Common-mode rejection ratio from 58dB to 82dBGo
- Changed Input impedance Differential-mode from 0.32 || 1 MΩ || pF to 0.77 || 0.3 MΩ || pFGo
- Changed the typical Input impedance common-mode from 3.5 || 1 MΩ || pF to 24 || 1.5MΩ || pFGo
- Changed Current output Sourcing and sinking from 70mA and –70mA to 170mA and –170mAGo
- Changed the typical closed-loop output impedance from 0.2Ω to 0.1ΩGo
- Changed Limiter Input Bias Current Magnitude from 16µA to 8µAGo
- Changed Limiter input impedance from 3.4 || 1 MΩ || pF to 1 || 7 MΩ || pFGo
- Changed typical Limiter feedthrough from –60dB to –92dBGo
- Deleted Bias current shift specificationGo
- Changed Limiter small signal bandwidth from 450MHz to 515MHzGo
- Changed Limiter slew rate from 100V/μs to 150V/μsGo
- Changed Limited step response overshoot from 55mV to 40mVGo
- Changed Limited step response recovery time from 3ns to 2.5nsGo
- Changed maximum Quiescent current from 14.9mA to 17.2mAGo
- Changed typical quiescent current from 14.3mA to 15.6mAGo
- Changed maximum quiescent current, TA = –40°C to +85°C from 15.3mA to 17.6mAGo
- Changed typical Power-supply rejection ratio from 70dB to 85dBGo
- Updated Typical Characteristics: VS = ±5V with new
die characteristicsGo
- Updated Typical Characteristics: VS = 5V with new
die characteristicsGo
- Updated Typical Application with data from Electrical
and Typical Characteristics
Go
Changes from Revision C (March 2006) to Revision D (December 2008)
- Changed minimum Storage temperature range from −40°C to −65°C.Go
Changes from Revision B (September 2003) to Revision C (March 2006)
- Changed board part number in the Demonstration Fixture
sectionGo