SCDS453E June   2024  – October 2025 TMUXS7614D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Source or Drain Current through Switch
    6. 5.6  Electrical Characteristics (Global)
    7. 5.7  Electrical Characteristics (±15V Dual Supply)
    8. 5.8  Switching Characteristics (±15V Dual Supply)
    9. 5.9  Electrical Characteristics (±20V Dual Supply)
    10. 5.10 Switching Characteristics (±20V Dual Supply)
    11. 5.11 Electrical Characteristics (+37.5V/–12.5V Dual Supply)
    12. 5.12 Switching Characteristics (+37.5V/–12.5V Dual Supply)
    13. 5.13 Electrical Characteristics (12V Single Supply)
    14. 5.14 Switching Characteristics (12V Single Supply)
    15. 5.15 SPI Timing Characteristics (2.7V to 5.5V)
    16. 5.16 SPI Timing Characteristics (1.8V to 2.7V)
    17. 5.17 Timing Diagrams
    18. 5.18 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  tON and tOFF Time
    5. 6.5  Break-Before-Make
    6. 6.6  Charge Injection
    7. 6.7  Off Isolation
    8. 6.8  Channel-to-Channel Crosstalk
    9. 6.9  Bandwidth
    10. 6.10 THD + Noise
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Operation
      2. 7.3.2 Rail-to-Rail Operation
      3. 7.3.3 1.8V Logic Compatible Inputs
      4. 7.3.4 Flat On-Resistance
      5. 7.3.5 Power-Up Sequence Free
    4. 7.4 SPI Operation
      1. 7.4.1 Address Mode
      2. 7.4.2 Burst Mode
      3. 7.4.3 Daisy Chain Mode
      4. 7.4.4 Error Detection
        1. 7.4.4.1 Address R/W Error Flag
        2. 7.4.4.2 SCLK Count Error Flag
        3. 7.4.4.3 CRC (Cyclic Redundancy Check) Enable and Error Flag
        4. 7.4.4.4 Clearing Error Flags
      5. 7.4.5 Software Reset
    5. 7.5 Device Functional Modes
    6. 7.6 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Recommended Reflow Profile
    4. 8.4 Thermal Considerations
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

4 Pin Configuration and Functions

TMUXS7614D ZEM Package, 30-Pin LGA (Top View)Figure 4-1 ZEM Package, 30-Pin LGA (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
D1 1 I/O Drain pin 1. Can be an input or output.
D2 2 I/O Drain pin 2. Can be an input or output.
D3 8 I/O Drain pin 3. Can be an input or output.
D4 9 I/O Drain pin 4. Can be an input or output.
D5 16 I/O Drain pin 5. Can be an input or output.
D6 17 I/O Drain pin 6. Can be an input or output.
D7 23 I/O Drain pin 7. Can be an input or output.
D8 24 I/O Drain pin 8. Can be an input or output.
GND 11, 29 P Ground (0V) reference. On TMUXS7614D, both GND pins are connected internally for flow through routing.
N.C. 20 - No internal connection. Can be shorted to GND or left floating.
S1 3 I/O Source pin 1. Can be an input or output.
S2 4 I/O Source pin 2. Can be an input or output.
S3 6 I/O Source pin 3. Can be an input or output.
S4 7 I/O Source pin 4. Can be an input or output.
S5 18 I/O Source pin 5. Can be an input or output.
S6 19 I/O Source pin 6. Can be an input or output.
S7 21 I/O Source pin 7. Can be an input or output.
S8 22 I/O Source pin 8. Can be an input or output.
SDI 27 I SPI Serial Data Input. Data is captured on the positive edge of SCLK.
SCLK 14, 26 I SPI Clock Input. Both SCLK pins are connected internally for flow through routing.
SDO 13 O SPI Serial Data Output. Data is shifted out on the negative edge of SCLK.
CS 15, 25 I SPI Chip Select Pin (active low). Both CS pins are connected internally for flow through routing.
RESET/VL 12, 28 P SPI Power Supply pin (1.8V – 5.5V) and hardware reset pin (active low). Pull the pin low to trigger a device hardware reset. After the hardware reset is complete, the SPI registers will be reset to their default state, and all the analog switches will be open. Both RESET/VL pins are connected internally for flow through routing. Connected to an integrated 0.1μF capacitor between VL and GND.
VDD 10, 30 P Positive power supply. This pin is the most positive power-supply potential. On TMUXS7614D, both VDD pins are connected internally for flow through routing. Connected to an integrated 0.1μF capacitor between VDD and GND.
VSS 5 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin should be connected to ground. Connected to an integrated 0.1μF capacitor between VSS and GND.
Thermal Pad — The thermal exposed pad is connected internally. It is recommended that the pad be tied to VSS for best performance.
(1) I = input, O = output, I/O = input and output, P = power.