SCDS461A November   2023  – January 2025 TMUX7348F-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics (Global)
    6. 6.6  ±15V Dual Supply: Electrical Characteristics
    7. 6.7  ±20 V Dual Supply: Electrical Characteristics
    8. 6.8  12 V Single Supply: Electrical Characteristics
    9. 6.9  36 V Single Supply: Electrical Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 7.5  Break-Before-Make Delay
    6. 7.6  Enable Delay Time
    7. 7.7  Transition Time
    8. 7.8  Fault Response Time
    9. 7.9  Fault Recovery Time
    10. 7.10 Fault Flag Response Time
    11. 7.11 Fault Flag Recovery Time
    12. 7.12 Charge Injection
    13. 7.13 Off Isolation
    14. 7.14 Crosstalk
    15. 7.15 Bandwidth
    16. 7.16 THD + Noise
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Flat ON- Resistance
      2. 8.3.2 Protection Features
        1. 8.3.2.1 Input Voltage Tolerance
        2. 8.3.2.2 Powered-Off Protection
        3. 8.3.2.3 Fail-Safe Logic
        4. 8.3.2.4 Overvoltage Protection and Detection
        5. 8.3.2.5 Adjacent Channel Operation During Fault
        6. 8.3.2.6 ESD Protection
        7. 8.3.2.7 Latch-Up Immunity
        8. 8.3.2.8 EMC Protection
      3. 8.3.3 Overvoltage Fault Flags
      4. 8.3.4 Bidirectional and Rail-to-Rail Operation
      5. 8.3.5 1.8 V Logic Compatible Inputs
      6. 8.3.6 Integrated Pull-Down Resistor on Logic Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Fault Mode
      3. 8.4.3 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4.1 Normal Mode

In Normal mode operation, signals of up to VFP and VFN can be passed through the switch from source (Sx) to drain (D or Dx) or from drain (D or Dx) to source (Sx). The address (Ax) pins and the enable (EN) pin determine which switch path to turn on (Table 8-1 provides more information). The following conditions must be satisfied for the switch to stay in the ON condition:

  • The difference between the primary supplies (VDD – VSS) must be higher or equal to 8 V. With a minimum VDD of 5 V.
  • VFP must be between 3 V and VDD, and VFN must be between VSS and 0 V.
  • The input signals on the source (Sx) or the drain (D or Dx) must be between VFP+ VT and VFN – VT.
  • The logic control (Ax and EN) must have selected the switch.