SCDS461A November   2023  – January 2025 TMUX7348F-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics (Global)
    6. 6.6  ±15V Dual Supply: Electrical Characteristics
    7. 6.7  ±20 V Dual Supply: Electrical Characteristics
    8. 6.8  12 V Single Supply: Electrical Characteristics
    9. 6.9  36 V Single Supply: Electrical Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 7.5  Break-Before-Make Delay
    6. 7.6  Enable Delay Time
    7. 7.7  Transition Time
    8. 7.8  Fault Response Time
    9. 7.9  Fault Recovery Time
    10. 7.10 Fault Flag Response Time
    11. 7.11 Fault Flag Recovery Time
    12. 7.12 Charge Injection
    13. 7.13 Off Isolation
    14. 7.14 Crosstalk
    15. 7.15 Bandwidth
    16. 7.16 THD + Noise
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Flat ON- Resistance
      2. 8.3.2 Protection Features
        1. 8.3.2.1 Input Voltage Tolerance
        2. 8.3.2.2 Powered-Off Protection
        3. 8.3.2.3 Fail-Safe Logic
        4. 8.3.2.4 Overvoltage Protection and Detection
        5. 8.3.2.5 Adjacent Channel Operation During Fault
        6. 8.3.2.6 ESD Protection
        7. 8.3.2.7 Latch-Up Immunity
        8. 8.3.2.8 EMC Protection
      3. 8.3.3 Overvoltage Fault Flags
      4. 8.3.4 Bidirectional and Rail-to-Rail Operation
      5. 8.3.5 1.8 V Logic Compatible Inputs
      6. 8.3.6 Integrated Pull-Down Resistor on Logic Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Fault Mode
      3. 8.4.3 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

TMUX7348F-EP PW Package,20-Pin TSSOP(Top View)Figure 5-1 PW Package,20-Pin TSSOP(Top View)
Table 5-1 Pin Functions: TMUX7348F-EP
PIN TYPE(1) DESCRIPTION
NAME NO.(2)
A0 1 I Logic control input address 0 (A0). The pin has a 4 MΩ internal pull-down resistor. This pin can also be used together with the specific fault pin (SF) to indicate which input is under fault. See Section 8.4.3 for more details.
A1 20 I Logic control input address 1 (A1). The pin has a 4 MΩ internal pull-down resistor. This pin can also be used together with the specific fault pin (SF) to indicate which input is under fault. See Section 8.4.3 for more details.
A2 19 I Logic control input address 2 (A2). The pin has a 4 MΩ internal pull-down resistor. This pin can also be used together with the specific fault pin (SF) to indicate which input is under fault. See Section 8.4.3 for more details.
D 8 I/O Drain pin. Can be an input or output. The drain pin is not overvoltage protected and shall remain within the recommended operating range.
EN 2 I Active high logic enable (EN) pin. The pin has a 4 MΩ internal pull-down resistor. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states. See Section 8.4.3 for more details.
FF 11 O General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is detected on any of the source (Sx) input pins. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1 kΩ pull-up resistor.
GND 18 P Ground (0 V) reference
S1 4 I/O Overvoltage protected source pin 1. Can be an input or output.
S2 5 I/O Overvoltage protected source pin 2. Can be an input or output.
S3 6 I/O Overvoltage protected source pin 3. Can be an input or output.
S4 7 I/O Overvoltage protected source pin 4. Can be an input or output.
S5 16 I/O Overvoltage protected source pin 5. Can be an input or output.
S6 15 I/O Overvoltage protected source pin 6. Can be an input or output.
S7 14 I/O Overvoltage protected source pin 7. Can be an input or output.
S8 13 I/O Overvoltage protected source pin 8. Can be an input or output.
SF 10 O Specific fault flag. This pin is an open drain output and is asserted low when overvoltage condition is detected on a specific pin, depending on the state of A0, A1, and A2 , as shown in Table 8-1. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1 kΩ pull-up resistor.
VDD 17 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VFN 9 P Negative fault voltage supply that determines the overvoltage protection triggering threshold on the negative side. Connect to VSS if the triggering threshold is to be the same as the device's negative supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VFN and GND.
VFP 12 P Positive fault voltage supply that determines the overvoltage protection triggering threshold on the positive side. Connect to VDD if the triggering threshold is to be the same as the device's positive supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VFP and GND.
VSS 3 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
(1) I = input, O = output, I/O = input and output, P = power
(2) Preview package