SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

3.1.2 McASP as Clock Peripheral

The following section details an example setup for a McASP where the bit clock and frame sync are configured as inputs.

Description GF MUX AUXCLK Source AHCLK Bit Clock Frame Sync
McASP clock peripheral Externally Generated Externally Generated

In this example, the McASP is being configured for a 48 kHz frame sync and TDM8 frame format with 32-bit words, resulting in a bit clock frequency of 12.288 MHz. The GF MUX and AHCLK settings do not matter in this case. The SDK driver must be configured to represent the expected frequency for bit clock and frame sync for proper audio data transmission.

Clock loss detection is not available for the McASP unless the AUDIO_EXT_REFCLK is utilized as detailed in Section 3.1.2.1.

McASP Clock Peripheral Figure 3-8 McASP Clock Peripheral