SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

4.2 McASP Topology for Multiple Devices in Single Clock Domain

The McASP will often be designed into a system where many audio devices share a single clock domain. For example, the TAS6754 is a 4-channel amplifier that can support TDM16. This means that a single McASP's bit clock, frame sync, and data pin can be shared by up to 4 amplifiers. The layout design of these three signals will impact the performance and reliability of the interface.

Figure 4-2 shows three different signal topologies for connecting a bit clock signal to four different amplifiers.

  • If the flyby topology is used, then the trace stubs created by each drop on the bus should be uniform in length and as short as possible to reduce reflections. This topology could lead to signal integrity issues depending on the clock frequency and trace length
  • A clock fanout buffer, such as the LMK1C1104, is the recommended approach for sharing a clock signal across multiple devices. By redriving the clock, the fanout buffer results in a clock signal with signal integrity that is near the performance of a point-to-point trace.
  • A balanced-T or star topology is where a single bus is split into branches that are equivalent in length for each of the devices. The branches that are created should be as short as possible with each stub created for a device being uniform in length.

Note: Regardless of topology, it is always recommended to include a series termination resistor on all McASP signals in close proximity the driver to surpress signal reflections and maintain signal integrity.
Clock Topologies for Multi-Device Audio Systems Figure 4-2 Clock Topologies for Multi-Device Audio Systems