SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

3.1 McASP Common Configurations

High-Level McASP Diagram Figure 3-2 High-Level McASP Diagram
Note: Each McASP has a transmit (TX) and receive (RX) domain. Figure 3-2 shows a single clock domain that is meant to be representative of either the TX or RX domain.

The McASP bit clock (ACLK) and frame sync (AFS) are both bidirectional such that the McASP can either be the clock controller or clock peripheral. The following sections detail all the available options for each clocking configuration.

Table 3-2 lists the most common use cases for configuring McASP. The AM275x SoC has many options for generating, sourcing, and receiving clocks for the audio data frame formatting.

Note: For bit clock and frame sync, internally generated refers to internally referenced signals that are output at the SoC level for McASP clock controller applications while externally generated means that the signals are configured as inputs at the SoC level for McASP clock peripheral applications.
Table 3-1 McASP Use Case Matrix
Description GF MUX AUXCLK Source AHCLK Bit Clock Frame Sync McASP Example
McASP clock controller with internal audio PLL reference Internal Audio PLL Internally Generated Internally Generated Internally Generated Figure 3-5 Figure 6-1
McASP clock controller with external AUXCLK reference AUDIO_EXT_REFCLK<n> Internally Generated Internally Generated Internally Generated Figure 3-6
McASP clock controller with external AHCLK reference Externally Generated Internally Generated Internally Generated Figure 3-7
McASP clock peripheral Externally Generated Externally Generated Figure 3-8
McASP clock peripheral with external AUXCLK reference AUDIO_EXT_REFCLK<n> Internally Generated Externally Generated Externally Generated Figure 3-9 Figure 6-2

Figure 3-2 shows a high-level overview of the different configuration options for McASP clocking while Figure 3-3 shows a more detailed view of the available options.

McASP Detailed Overview Figure 3-3 McASP Detailed Overview