SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

6.1 Audio Playback with Internal Audio PLL for Two Clock Domains

Figure 6-1 shows a simple example of how the McASP can use a single internal reference to send and receive audio data across multiple domains. The McASP is operating in asynchronous mode, but because the root clock source is the same for the transmit and receive domain, there is no risk of buffer overrun or underrun (as long as the audio data frame formatting is the same on the input and output).

For this system, the Audio PLL uses HFOSC1 to generate a high frequency audio clock reference. The high speed divider (PLL4_HSDIV0) divides the high frequency reference to 49.152MHz for the AUXCLK input. In this case, the TX and RX domains have AHCLK, ACLK, and AFS all configured to be internally generated.

The audio data frame is four audio channels for a single TDM4 stream and, assuming that the word depth is 32 bits, then the bit clock can be calculated based on the product of 4 channels of 32 bit words that are sampled at 48kHz = 4*32*48,000 = 6.144 MHz.

ADC DAC Audio Playback Figure 6-1 ADC DAC Audio Playback