SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

7 Key Audio System Design Takeaways

  • The McASP has two modes of operation for clock synchronization:
    • Sync mode: where the ACLKX and AFSX signals are internally routed to ACLKR and AFSR and all audio data is sent and received with a single clock domain.
    • Asynchronous mode: The TX and RX clock domains are independent of each other and the audio data clock domains are determined by the serializer IO direction.

  • Multizone audio systems ideally have one clock reference for all generated bit clocks and frame syncs in order to avoid audio data buffering issues. The clock reference can either be provided by an internal audio reference or an external source.
    • If the AM275x is providing the internal reference for the audio system, then either the McASPs need to be configured to internally reference the Audio PLL or the Audio PLL must be provided to external devices for bit clock and frame sync generation.
    • If an external source is providing the audio clock reference for the audio system, then either the McASPs need to be configured to internally reference an AUDIO_EXT_REFCLK input or they need to have the bit clock and frame syncs configured to be externally generated.
      • If the external source does not have a device level high-frequency reference, then the bit clock must also be routed to an AUDIO_EXT_REFCLK input to enable other McASP instances with the same reference.

  • If the multizone audio system requires multiple audio clock references for different domains, then the ASRC must be used, even if the bit clock and frame sync frequencies are same between two clock domains. If the ASRC is not used to bridge two clock domains with different reference sources, then the clock jitter between the domains will introduce audio data buffer overrun or underrun issues.
  • Each ASRC module can convert the sample rate of up to 16 channels. The number of ASRC modules in the AM275x depends on the device performance grade. AM275x with the operating performance point A or B only have one ASRC while C/D/E/F all have two ASRC modules.
  • Carefully review all bootmode signals that are shared with McASP signals to ensure that there aren't any unnecessary trace stubs introduced on the clock or data signal lines.
  • For clock and data signals that are shared across multiple devices, ensure that the layout topology does not impact the performance of the signal.
    • Always simulate the signal with the proposed layout topology to ensure the reliability and integrity of the audio data transfers.