SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source

The following section details an example setup for a McASP where the bit clock and frame sync are configured as outputs and generated using an external source via AUDIO_EXT_REFCLK as a clock reference directly to the AHCLK.

Description GF MUX AUXCLK Source AHCLK Bit Clock Frame Sync
McASP clock controller with external AHCLK input reference Externally Generated Internally Generated Internally Generated

In this example, the McASP is being configured for a 48 kHz frame sync and TDM8 frame format with 32 bit words, resulting in a bit clock frequency of 12.288 MHz. The GF MUX and AUXCLK are not considered when AHCLK is configured to be externally generated. Each AHCLK has a unique mux to select different external sources. The AHCLK mux is configured to point to the AUDIO_EXT_REFCLK0 source that is 24.576 MHz from an external driver. The SDK driver sets the ACLK divider based upon the number of slots, frame sync frequency, and ratio between frame sync and AHCLK.

When the AHCLK is externally generated then the AHCLK can't be output on the AUDIO_EXT_REFCLK.

Clock loss detection is not available for the McASP if the AHCLK is externally generated.

McASP Clock Controller with AUDIO_EXT_REFCLK0 AHCLK Reference Figure 3-7 McASP Clock Controller with AUDIO_EXT_REFCLK0 AHCLK Reference