SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input

The following section details an example setup for a McASP where the bit clock and frame sync are configured as inputs.

Description GF MUX AUXCLK Source AHCLK Bit Clock Frame Sync
McASP clock peripheral with an external AUXCLK reference AUDIO_EXT_REFCLK<n> Externally Generated Externally Generated Externally Generated

In this example, the McASP is being configured for a 48 kHz frame sync and TDM8 frame format with 32-bit words resulting, in a bit clock frequency of 12.288 MHz. The GF MUX is configured to point to the external reference mux which is selecting AUDIO_EXT_REFCLK0 source that is 24.576 MHz from an external driver. The SDK driver sets the AHCLK and ACLK dividers but they are not used as ACLK and AFS is externally driven.

When the AHCLK is internally generated then the AHCLK can optionally be output on any of the AUDIO_EXT_REFCLK pins to provide a system clock reference output.

Additionally, the clock loss detection feature of the McASP is enabled with an internally generated AHCLK. For additional information on the clock loss detection for the McASP, refer to the Clock Failure Detection chapter within the MCASP Error Reporting section of the AM275x Technical Reference Manual.

McASP Clock Peripheral with AUDIO_EXT_REFCLK AUXCLK Reference Figure 3-9 McASP Clock Peripheral with AUDIO_EXT_REFCLK AUXCLK Reference