SDAA014 November   2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Abstract
  3.   How to Use this Document
  4.   Trademarks
  5. 1Digital Audio Formats
    1. 1.1 I2S
    2. 1.2 TDM
  6. 2McASP Overview
  7. 3McASP Connections for AM275x
    1. 3.1 McASP Common Configurations
      1. 3.1.1 McASP as a Clock Controller
        1. 3.1.1.1 Clocks Generated using the Internal Audio PLL
        2. 3.1.1.2 Clocks Generated using the AUDIO_EXT_REFCLK AUXCLK Source
        3. 3.1.1.3 Clocks Generated using the AUDIO_EXT_REFCLK AHCLK Source
      2. 3.1.2 McASP as Clock Peripheral
        1. 3.1.2.1 Clock Externally Generated with AUDIO_EXT_REFCLK Input
  8. 4McASP Layout Considerations
    1. 4.1 McASP Signals Shared with Bootmode Logic
    2. 4.2 McASP Topology for Multiple Devices in Single Clock Domain
  9. 5ASRC Overview
  10. 6McASP Practical Examples
    1. 6.1 Audio Playback with Internal Audio PLL for Two Clock Domains
    2. 6.2 Audio Playback with External Clock Source and McASP SYNC mode
    3. 6.3 Audio Playback with ASRC Bridging Two Clock Domains
  11. 7Key Audio System Design Takeaways
  12. 8References

3.1.1 McASP as a Clock Controller

If the McASP is configured as a clock controller, then the bit clock and frame sync signals are configured as outputs. The SDK driver defines bit clock and frame sync as outputs when the source is set to Internally Generated. This means that the bit clock is internally generated from the high clock and that the frame sync is generated based on the bit clock. The high clock of a TX or RX domain, as well as the McASP AUXCLK, feature many options to best fit audio system requirements.

The AUXCLK is a single clock reference that can be sourced to both the TX and RX domains. For the AM275x, each McASP AUXCLK input is tied to a glitch-free (GF) clock mux that selects between a local and external clock reference. The local reference for AUXCLK is either the audio PLL (PLL4) clock input or one of the PLL's high speed divider outputs. The external clock reference is any of the AUDIO_EXT_REFCLK inputs.

When the AHCLK is internally generated, then the AHCLK can be routed as an output on any of the AUDIO_EXT_REFCLK pins for a high-frequency reference.

Note: The SDK refers to the high clock source (AHCLK) as being Internally Generated when the AUXCLK is being used to generate the AHCLK. This can be confusing since the AUXCLK input has the option to be externally generated if the GF mux is configured for the AUDIO_EXT_REFCLK mux reference option.
McASP Controller with AUXCLK Source Figure 3-4 McASP Controller with AUXCLK Source