SDAA132 December   2025 MSPM33C321A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM33C Hardware Design Check List
  5. 2 Power Supplies in MSPM33C Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
    5. 2.5 Recommended Decoupling Circuit for VBAT
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Oscillators
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 COMP Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 MCAN Design Considerations
    4. 7.4 I2C and SPI Design Considerations
    5. 7.5 I2S/TDM Design Considerations
    6. 7.6 QSPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High-Speed GPIOs (HSIO)
    4. 8.4 High-Drive GPIOs (HDIO)
    5. 8.5 Communicate With a 1.8V Device Without a Level Shifter
    6. 8.6 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11Summary
  15. 12References

6.1 ADC Design Considerations

MSPM33C devices have a 12-bit, up to 8Msps, analog-to-digital converter (ADC). The ADC implements a 12-bit SAR core, sample or conversion mode control, and up to 12 independent conversion-and-control buffers.

ADC Input NetworkFigure 6-1 ADC Input Network

To achieve the desired conversion speed and keep high accuracy, make sure there is proper sampling time in hardware designs. Sampling (sample-and-hold) time determines how long to sample a signal before digital conversion. During sample time, an internal switch allows the input capacitor to be charged. The required time to fully charge the capacitor is dependent on the external analog front-end (AFE) connected to the ADC input pin. Figure 6-1 shows a typical ADC model of an MSPM33C MCU. The Rin and CS/H values can be obtained from the device-specific data sheet. Understand the AFE drive capability and calculate the minimum sampling time required to sample the signal. The resistance of RPar and Rin affects tsample. Equation 1 can be used to calculate a conservative value of the minimum sample time tsample for an n-bit conversion:

Equation 1. tsample ≥ (Rpar + Rin) × ln(2n+2) × (CS/H + C1 + CPar)

To evaluate continuous high speed (8Msps) ADC performance, TI recommends adding an external buffer to make sure of sufficient signal source drive capability. As a design reference, see the LP-MSPM33C321A hardware design.