SDAA132 December   2025 MSPM33C321A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM33C Hardware Design Check List
  5. 2 Power Supplies in MSPM33C Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
    5. 2.5 Recommended Decoupling Circuit for VBAT
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Oscillators
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 COMP Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 MCAN Design Considerations
    4. 7.4 I2C and SPI Design Considerations
    5. 7.5 I2S/TDM Design Considerations
    6. 7.6 QSPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High-Speed GPIOs (HSIO)
    4. 8.4 High-Drive GPIOs (HDIO)
    5. 8.5 Communicate With a 1.8V Device Without a Level Shifter
    6. 8.6 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11Summary
  15. 12References

1 MSPM33C Hardware Design Check List

Table 1-1 describes the main contents that must be checked during the MSPM33C hardware design process. The following sections provide more details.

Table 1-1 MSPM33C Hardware Design Check List
PinDescriptionRequirements
VDDPower supply positive pinPlace 10µF and 100nF capacitors between VDD and VSS and keep those part close to VDD and VSS pins.
VSSPower supply negative pin
VCORECore voltage (typical: 1.35V)Connect a 2.2μF capacitor to VSS. Do not supply any voltage or apply any external load to the VCORE pin.
VBAT Battery Backup Supply Connect a 1μF capcaitor to VSS. Only required if using peripherals in the low frequency subsystem (LFSS).
NRSTReset pinConnect an external 47kΩ pullup resistor with a 10nF to 100nF pulldown capacitor. Adding a capacitor of appropriate capacitance to the reset pin can suppress transient interference caused by ESD, thereby reducing the risk of accidental reset.
VREF+Voltage reference power supply - external reference input
  • When using VREF, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source.
  • Leaving open is OK if the application does not use the voltage reference.
VREF-Voltage reference ground supply - external reference input
SWCLKSerial wire clock from debug probeInternal pulldown to VSS, does not need any external part.
SWDIOBidirectional (shared) serial wire dataInternal pullup to VDD, does not need any external part.
PA18Default BSL invoke PinKeep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.)
GPIO pinsGeneral-purpose I/OSet corresponding pin functions to GPIO. (PINCMx.PF = 0x1)
Unused PinsGeneral-purpose I/OConfigure unused pins to output low or input with internal pullup or pulldown resistor.
Thermal PadThermal pad on QFN packageThe heat of the pad is transferred to the continuous copper plane (such as the GND Plane) of the PCB through the via. The larger the copper area, the better the heat dissipation effect.
Note: For any unused pin with a function that is shared with general-purpose I/O, follow the guidelines in Section 8.6.

TI recommends connecting a combination of a 10μF and a 0.1nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins. Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that for decouple (within a few millimeters).

The NRST reset pin is required to connect an external 47kΩ pullup resistor with a 10nF pulldown capacitor.

For devices support external crystals, external bypass capacitors for the crystal oscillator pins are required when using external crystals.

A 2.2µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground.

MSPM33C Typical Application Schematic Figure 1-1 MSPM33C Typical Application Schematic