SDAA132 December   2025 MSPM33C321A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM33C Hardware Design Check List
  5. 2 Power Supplies in MSPM33C Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
    5. 2.5 Recommended Decoupling Circuit for VBAT
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Oscillators
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 COMP Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 MCAN Design Considerations
    4. 7.4 I2C and SPI Design Considerations
    5. 7.5 I2S/TDM Design Considerations
    6. 7.6 QSPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High-Speed GPIOs (HSIO)
    4. 8.4 High-Drive GPIOs (HDIO)
    5. 8.5 Communicate With a 1.8V Device Without a Level Shifter
    6. 8.6 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11Summary
  15. 12References

8.2 GPIO Current Sink and Source

Table 8-2 MSPM33C GPIO Absolute Maximum Ratings
MINNOMMAXUNIT
VDDSupply voltage1.623.6V
VCOREVoltage on VCORE pin 1.35V
CVDDCapacitor placed between VDD and VSS 10uF
CVCORECapacitor placed between VCORE and VSS 470nF
TAAmbient temperature, T version–40105°C
Ambient temperature, S version–40125
TJMax junction temperature, T version125°C
TJMax junction temperature, S and Q versions130°C
fMCLK(PD1 bus clock)MCLK, CPUCLK, ULPCLK frequency with 2 flash wait state 80MHz
MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 48
MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 24
fULPCLK(PD0 bus clock)ULPCLK frequency40MHz
Note:
  • The total current of I/O must be less than the maximum value of IVDD.
  • HDIO, ODIO, and HSIO are patched in a fixed pin, see to the device data sheet.

SDIO and HSIO are able to sink or source a maximum current of 6mA (typical), which is sufficient to drive a typical LED. For larger current loading, use HDIO (maximum current of 20mA (typical)). However, the total combined current must be less than IVDD (80mA typical).