SDAA170 September   2026 TPS61383-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Requirement and System Structure
    1. 2.1 Design Requirements
    2. 2.2 System Structure
      1. 2.2.1 Centralized E‑Latch System
      2. 2.2.2 Distributed E‑Latch System
  6. 3Power Train
    1. 3.1 Integrated E-Latch Power Train with TPS61383-Q1
      1. 3.1.1 Super Capacitor Charger Function Introduction
      2. 3.1.2 Boost Function Introduction
      3. 3.1.3 Super Capacitor Bleeding
    2. 3.2 Hardware Design Procedure
      1. 3.2.1 Selecting the External MOSFET
      2. 3.2.2 Inductor Selection
      3. 3.2.3 Capacitor in Super Capacitor Side
      4. 3.2.4 Boost Output Capacitor
      5. 3.2.5 Loop Compensation Design
      6. 3.2.6 Key Considerations
    3. 3.3 Software Initial Process
  7. 4Super Capacitor Energy Modeling Basis and Selection
    1. 4.1 Discharge Profile and Cut-off Voltage
    2. 4.2 Super Capacitor Discharge Energy Modeling
    3. 4.3 Calculation Example
    4. 4.4 Super Capacitor Excel Calculation Tool
  8. 5Super Capacitor Management
    1. 5.1 Voltage Monitoring with BQ76907-Q1
    2. 5.2 Cell Balancing with BQ76907-Q1
      1. 5.2.1 Balancing Strategy
      2. 5.2.2 I2C Implementation
      3. 5.2.3 Cell Balancing Current
      4. 5.2.4 Low-Side Protection Circuit Design Considerations
    3. 5.3 Super Capacitor Health Detection: Combined Solution of TPS61383-Q1 and BQ76907-Q1
  9. 6Control Unit and Communication
    1. 6.1 Control Unit Design Consideration
    2. 6.2 SBC Selection
  10. 7Execution Unit
    1. 7.1 Motor Driver Structure
    2. 7.2 Motor Driver Design Considerations
  11. 8Summary
  12. 9References

4.3 Calculation Example

With the previous analysis on super capacitor, calculate the requirements on the super capacitor. This section gives an example on calculating minimum Cscap. Assume an e-latch system with the following design targets:

Table 4-1 Design Requirement Example
Item Parameter
Cell Number 3s
Super Capacitor Voltage 2.5V per cell, 7.5V total
Super Capacitor Internal Resistance 30mΩ per cell, 90mΩ total
Load Power 72W (12V, 6A)
Load Duration 10 locks, 100ms each, 1s total time
Boost Efficiency 90%
Boost Current Limit 25A
  1. Calculate VCL
    Equation 30. V C U T _ O F F = M A X ( P O U T η B S T I L I M + I L I M R S C A P ,   2 P O U T R S C A P ) = M A X ( 72 W 0 . 9 × 25 A + 25 A × 90 m Ω ,   2 × 72 W × 90 m Ω ) = M A X ( 5 . 45 V ,   3 . 6 V ) = 5 . 45 V
  2. Calculate parameter b and k
    Equation 31. b = 4 V o u t I o u t R S C A P η B S T = 28 . 8 W . Ω
    Equation 32. k = [ V C H 2 - V C L 2 + V C L V C L 2 - b - V C H V C H 2 - b + b ( ln ⁡ ( V C H + V C H 2 - b ) - ln ⁡ ( V C L + V C L 2 - b ) ) ] / 4 = 3 . 064 V 2
  3. Calculate Cmin
    Equation 33. C m i n = 2 V o u t I o u t T η B S T ( V C H 2 - V C L 2 ) - 2 k = 2 × 72 W × 1 s 0 . 9 ( 7 . 5 2 - 5 . 45 2 ) - 2 × 3 . 064 V 2 = 8 . 1 F
  4. Verifying Results

    According to the previous calculation results, a 25F per cell (8.333F for total of three cell) super capacitor is selected. So the maximum energy that can be discharged is:

    Equation 34. E S C A P = 1 2 C S C A P V C H 2 - 1 2 C S C A P V C L 2 = 110 . 61 J

    The energy consumption for load is:

    Equation 35. E l o a d = V o u t I o u t T = 72 J

    The loss on TPS61383 is:

    Equation 36. l o s s B S T = E l o a d ( 1 η B S T - 1 ) = 8 J

    The loss on super capacitor internal resistor is:

    Equation 37. l o s s R S C A P = k   C S C A P = 2 . 553 J

    The total energy consumption is:

    Equation 38. E t o t a l = E l o a d + l o s s B S T + l o s s R S C A P = 82.533 J

    The energy margin is:

    Equation 39. E m a r g i n = E S C A P - E t o t a l = 27 . 4 J