SDAA170 September   2026 TPS61383-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Requirement and System Structure
    1. 2.1 Design Requirements
    2. 2.2 System Structure
      1. 2.2.1 Centralized E‑Latch System
      2. 2.2.2 Distributed E‑Latch System
  6. 3Power Train
    1. 3.1 Integrated E-Latch Power Train with TPS61383-Q1
      1. 3.1.1 Super Capacitor Charger Function Introduction
      2. 3.1.2 Boost Function Introduction
      3. 3.1.3 Super Capacitor Bleeding
    2. 3.2 Hardware Design Procedure
      1. 3.2.1 Selecting the External MOSFET
      2. 3.2.2 Inductor Selection
      3. 3.2.3 Capacitor in Super Capacitor Side
      4. 3.2.4 Boost Output Capacitor
      5. 3.2.5 Loop Compensation Design
      6. 3.2.6 Key Considerations
    3. 3.3 Software Initial Process
  7. 4Super Capacitor Energy Modeling Basis and Selection
    1. 4.1 Discharge Profile and Cut-off Voltage
    2. 4.2 Super Capacitor Discharge Energy Modeling
    3. 4.3 Calculation Example
    4. 4.4 Super Capacitor Excel Calculation Tool
  8. 5Super Capacitor Management
    1. 5.1 Voltage Monitoring with BQ76907-Q1
    2. 5.2 Cell Balancing with BQ76907-Q1
      1. 5.2.1 Balancing Strategy
      2. 5.2.2 I2C Implementation
      3. 5.2.3 Cell Balancing Current
      4. 5.2.4 Low-Side Protection Circuit Design Considerations
    3. 5.3 Super Capacitor Health Detection: Combined Solution of TPS61383-Q1 and BQ76907-Q1
  9. 6Control Unit and Communication
    1. 6.1 Control Unit Design Consideration
    2. 6.2 SBC Selection
  10. 7Execution Unit
    1. 7.1 Motor Driver Structure
    2. 7.2 Motor Driver Design Considerations
  11. 8Summary
  12. 9References

5.2.3 Cell Balancing Current

Properly setting the battery balancing current is important for optimizing the cell-balancing function. The balancing current magnitude is jointly determined by the on-chip NMOS FET and the resistance value of the input filter resistor. The recommended minimum value of the input filter resistors when using internal balancing is 20Ω. This results in a balancing current of approximately 35mA.

Equation 40. IB_alance=VCELL2×Rn+RCB=4.22×20+80=35mA
If OEM require a faster balancing speed than 35mA , external balancing bypass circuit can be implemented. One feasible solution is to deploy external FETs or BJTs. More design details can refer to Cell Balancing With BQ7690x Battery Monitors.