SDAA513 August   2026 AM2432 , AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62L , AM62P , AM62P-Q1 , DRA821U , DRA821U-Q1 , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1  Why ECC Error Injection Testing is Required
    2. 2.2  DDR Inline ECC Protection Mechanism
      1. 2.2.1 Multi-Phase ECC Protection
    3. 2.3  Offline Error Injection
    4. 2.4  Online Error Injection
      1. 2.4.1 Method 1: ESM Fault Injection
      2. 2.4.2 Method 2: Reserved DDR Validation Region
    5. 2.5  Single-Bit Error Validation
    6. 2.6  Double-Bit Error Validation
    7. 2.7  Multi-Phase ECC Validation
    8. 2.8  Verification Using ECC Error Logs
    9. 2.9  Verification Using ESM
    10. 2.10 Recommended Validation Strategies
      1. 2.10.1 Automotive Systems
      2. 2.10.2 Industrial Systems
  6. 3Summary
  7. 4References

2.2.1 Multi-Phase ECC Protection

DDR accesses occur as burst transactions consisting of multiple phases.

A conventional SECDED implementation protects individual data words. DDR Inline ECC implements Multi-Phase ECC protection that extends coverage beyond individual phases.

This mechanism provides additional protection against:

  • Address failures
  • Command failures
  • Address aliasing
  • Burst corruption
  • Large-scale memory corruption

As a result, DDR Inline ECC increases diagnostic coverage compared with conventional SECDED-only implementations.