SLAAED5A June   2023  – September 2025 AFE11612-SEP , OPA4H199-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. LDMOS and GaN Power Amplifier FET PA Basics
  5. VGS Compensation
  6. Sequencing
  7. An Integrated PA Biasing Solution
  8. Negative Biasing for GaN PAs
  9. Fast Switching for TDD Applications
  10. VDRAIN Switching Circuit
  11. Controlled Gate-Sequencing Circuit
  12. VDRAIN Monitoring
  13. 10External Negative Power Supply Monitoring
  14. 11PA Temperature Monitoring
  15. 12Summary
  16. 13References
  17. 14Revision History

VDRAIN Switching Circuit

The VDRAIN protection circuit uses NMOS and PMOS transistors to disable the voltage being applied to the PA drain. This PA_ON circuit functions as a high-voltage switch. The VDRAIN needs to be disabled at key times during startup, shutdown, and alarm events. This is achieved in this design by an NMOS and PMOS circuit. When the PA_ON voltage is applied to the NMOS gate, the circuit turns on to allow VDRAIN through the PMOS.

 VDRAIN Enable
                        CircuitFigure 7-1 VDRAIN Enable Circuit
 VDRAIN Enable
                        PlotFigure 7-2 VDRAIN Enable Plot