SLAAER4 March   2025 AFE781H1 , AFE782H1 , AFE881H1 , AFE882H1 , DAC8740H , DAC8741H , DAC8742H

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 The 4-20mA Loop
    2. 1.2 The HART Protocol
      1. 1.2.1 Adding HART to the 4-20mA Loop
      2. 1.2.2 HART FSK
  5. 2AFE882H1 EVM-Based HART Transmitter
    1. 2.1 AFE882H1 HART Modem
    2. 2.2 AFE882H1 Evaluation Module
    3. 2.3 HART Transmitter Construction
      1. 2.3.1 Detailed Schematic
        1. 2.3.1.1 Input Protection
        2. 2.3.1.2 Start Up With Low-Dropout Regulator
        3. 2.3.1.3 Voltage-to-Current Stage
        4. 2.3.1.4 Voltage-to-Current Calculation
        5. 2.3.1.5 HART Signal Transmission
        6. 2.3.1.6 HART Input Protection
        7. 2.3.1.7 HART Transmitter Board
        8. 2.3.1.8 Current Consumption
      2. 2.3.2 HART Protocol Stack
  6. 3HART Testing and Registration
    1. 3.1  HART History and the FieldComm Group
    2. 3.2  HART Testing Overview
      1. 3.2.1 HART Protocol Specifications
      2. 3.2.2 HART Protocol Test Specifications
      3. 3.2.3 Field Transmitter Device Testing
    3. 3.3  HART Test Equipment
    4. 3.4  HART Physical Layer Testing
      1. 3.4.1 FSK Sinusoid Test
      2. 3.4.2 Carrier Start and Stop Time Tests
      3. 3.4.3 Carrier Start and Stop Transient Tests
      4. 3.4.4 Output Noise During Silence
      5. 3.4.5 Analog Rate of Change Test
      6. 3.4.6 Receive Impedance Test
      7. 3.4.7 Noise Sensitivity Test
      8. 3.4.8 Carrier Detect Test
    5. 3.5  Data Link Layer Tests
      1. 3.5.1 Data Link Layer Test Specifications
      2. 3.5.2 Data Link Layer Test Logs
    6. 3.6  Universal Command Tests
    7. 3.7  Common-Practice Command Tests
    8. 3.8  Device Specific Command Tests
    9. 3.9  HART Protocol Test Submission
    10. 3.10 HART Registration
  7. 4Summary
  8. 5Acknowledgments
  9. 6References

2.3.1 Detailed Schematic

Figure 2-6 shows a schematic of the AFE882H1-FE-EVM board. The schematic shows the 24V loop power connection on the right side of the figure. Input protection is placed between the input terminals and the transmitter circuit. The positive loop connects to a startup circuit for the board and powers an LDO. This LDO powers the AFE device, op-amps, and V-to-I control.

2-Wire Transmitter Design Using an AFE882H1 Circuit Schematic Figure 2-6 2-Wire Transmitter Design Using an AFE882H1 Circuit Schematic

The AFE882H1 controls the loop current through the V-to-I section. The DAC voltage has an output range from 0V to 2.5V. The output is sent through a V-to-I converter stage using an OPA333 and an NPN bipolar junction transistor (BJT) that controls the loop current. In the constructed transmitter, the digital signals of the AFE882H1 are driven by an MSP430FR5969 LaunchPad. The DAC-LP-DBE bridges the digital signals between the AFE882H1-FE-EVM and the LaunchPad and also powers the LaunchPad from an LDO sourced by the loop