SLASEE9C September   2017  – May 2025 TPA3221

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Characteristics (BTL)
    7. 6.7 Audio Characteristics (PBTL)
    8.     Typical Characteristics, BTL Configuration, AD-mode
    9.     Typical Characteristics, PBTL Configuration, AD-mode
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Internal LDO
        1. 8.3.1.1 Input Configuration, Gain Setting And Controller/Peripheral Operation
      2. 8.3.2 Gain Setting And Controller / Peripheral Operation
      3. 8.3.3 AD-Mode and HEAD-Mode PWM Modulation
      4. 8.3.4 Oscillator
      5. 8.3.5 Input Impedance
      6. 8.3.6 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Powering Up
        1. 8.4.1.1 Startup Ramp Time
      2. 8.4.2 Powering Down
        1. 8.4.2.1 Power Down Ramp Time
      3. 8.4.3 Device Reset
      4. 8.4.4 Device Soft Mute
      5. 8.4.5 Device Protection System
        1. 8.4.5.1 Overload and Short Circuit Current Protection
        2. 8.4.5.2 Signal Clipping and Pulse Injector
        3. 8.4.5.3 DC Speaker Protection
        4. 8.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.5.5 Overtemperature Protection OTW and OTE
        6. 8.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.5.7 Fault Handling
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 BST capacitors
          4. 9.2.1.2.4 PCB Material Recommendation
      2. 9.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
        1. 9.2.2.1 Design Requirements
      3. 9.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 9.2.3.1 Design Requirements
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
        1. 9.3.1.1 VDD Supply
        2. 9.3.1.2 AVDD and GVDD Supplies
        3. 9.3.1.3 PVDD Supply
        4. 9.3.1.4 BST Supply
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 BTL Application Printed Circuit Board Layout Example
        2. 9.4.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
        3. 9.4.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

The TPA3221 is available in a thermally enhanced TSSOP package.

The package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heat sink.

TPA3221 DDV PackageHTSSOP 44-Pin(Top View)Figure 5-1 DDV PackageHTSSOP 44-Pin(Top View)
Table 5-1 Pin Functions
NAME NO. I/O(1) DESCRIPTION
HEAD 11 I 0 = AD, 1 = HEAD. Refer to: Section 8.3.3
AVDD 21 P AVDD voltage supply. Refer to: Section 8.3.1, Section 9.3.1.2
BST1_M 43 P OUT1_M HS bootstrap supply (BST), 0.033μF capacitor to OUT1_M required.
Refer to: Section 9.2.1.2.3
BST1_P 44 P OUT1_P HS bootstrap supply (BST), 0.033μF capacitor to OUT1_P required.
Refer to: Section 9.2.1.2.3
BST2_M 23 P OUT2_M HS bootstrap supply (BST), 0.033μF capacitor to OUT2_M required.
Refer to: Section 9.2.1.2.3
BST2_P 24 P OUT2_P HS bootstrap supply (BST), 0.033μF capacitor to OUT2_P required.
Refer to: Section 9.2.1.2.3
CMUTE 17 P Mute and Startup Timing Capacitor. Connect a 33nF capacitor to GND. Refer to: Section 8.4.3
FAULT 4 O Shutdown signal, open drain; active low. Refer to: Section 8.3.6
FREQ_ADJ 14 O Oscillator frequency programming pin. Refer to: Section 8.3.4
GAIN/SLV 2 I Closed loop gain and controller/peripheral programming pin.
Refer to: Section 8.3.1.1
GND 5, 6, 7, 18, 19, 20, 25, 26, 33, 34, 41, 42 P Ground
GVDD 22 P Gate drive supply. Refer to: Section 8.3.1, Section 9.3.1.2
IN1_M 9 I Negative audio input for channel 1
IN1_P 8 I Positive audio input for channel 1
IN2_M 16 I Negative audio input for channel 2
IN2_P 15 I Positive audio input for channel 2
OSCM 12 I/O Oscillator synchronization interface.
Refer to: Section 8.3.1.1
OSCP 13 I/O Oscillator synchronization interface.
Refer to: Section 8.3.1.1
OTW_CLIP 3 O Clipping warning and Over-temperature warning; open drain; active low.
Refer to: Section 8.3.6
OUT1_M 35 O Negative output for channel 1
OUT1_P 39, 40 O Positive output for channel 1
OUT2_M 27, 28 O Negative output for channel 2
OUT2_P 32 O Positive output for channel 2
PVDD 29, 30, 31, 36, 37, 38 P PVDD supply. Refer to: Section 9.2.1.2.2, Section 9.3.1.3
RESET 10 I Device reset Input; active low. Refer to: Section 8.4.5.7, Section 8.4.1, Section 8.4.2
VDD 1 P Input power supply. Refer to: Section 8.3.1, Section 9.3.1.1
PowerPad™ P Ground, connect to grounded heatsink. Placed on top side of device.
(1) I=Input, O=Output, I/O= Input/Output, P=Power
Table 5-2 Mode Selection Pins
MODE PINS(2) INPUT MODE(1) OUTPUT CONFIGURATION DESCRIPTION
IN2_M IN2_P HEAD
X X 0 1N/2N + 1 2 × BTL Stereo, BTL output configuration, AD mode modulation
X X 1 1N/2N + 1 2 × BTL Stereo, BTL output configuration, HEAD mode modulation
0 0 0 1N/2N + 1 1 x PBTL Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, AD mode modulation
0 0 1 1N/2N + 1 1 x PBTL Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, HEAD mode modulation
1 1 0 1N/2N + 1 1 x BTL Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode modulation
1 1 1 1N/2N + 1 1 x BTL Mono, BTL configuration. OUT1_M and OUT1_P active, HEAD mode modulation
(1) 2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control ( RESET) input pins.
(2) X refers to inputs connected through AC coupling capacitor, 0 refers to logic low (GND), 1 refers to logic high (AVDD).