SLASEE9C September   2017  – May 2025 TPA3221

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Characteristics (BTL)
    7. 6.7 Audio Characteristics (PBTL)
    8.     Typical Characteristics, BTL Configuration, AD-mode
    9.     Typical Characteristics, PBTL Configuration, AD-mode
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Internal LDO
        1. 8.3.1.1 Input Configuration, Gain Setting And Controller/Peripheral Operation
      2. 8.3.2 Gain Setting And Controller / Peripheral Operation
      3. 8.3.3 AD-Mode and HEAD-Mode PWM Modulation
      4. 8.3.4 Oscillator
      5. 8.3.5 Input Impedance
      6. 8.3.6 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Powering Up
        1. 8.4.1.1 Startup Ramp Time
      2. 8.4.2 Powering Down
        1. 8.4.2.1 Power Down Ramp Time
      3. 8.4.3 Device Reset
      4. 8.4.4 Device Soft Mute
      5. 8.4.5 Device Protection System
        1. 8.4.5.1 Overload and Short Circuit Current Protection
        2. 8.4.5.2 Signal Clipping and Pulse Injector
        3. 8.4.5.3 DC Speaker Protection
        4. 8.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.5.5 Overtemperature Protection OTW and OTE
        6. 8.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.5.7 Fault Handling
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 BST capacitors
          4. 9.2.1.2.4 PCB Material Recommendation
      2. 9.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
        1. 9.2.2.1 Design Requirements
      3. 9.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 9.2.3.1 Design Requirements
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
        1. 9.3.1.1 VDD Supply
        2. 9.3.1.2 AVDD and GVDD Supplies
        3. 9.3.1.3 PVDD Supply
        4. 9.3.1.4 BST Supply
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 BTL Application Printed Circuit Board Layout Example
        2. 9.4.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
        3. 9.4.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

PVDD_X = 30V, VDD = 5V, GVDD = 5V, TC (Case temperature) = 75 °C, fS = 600kHz, unless otherwise specified.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
AVDDVoltage regulator. Only used as reference node when supplied by internal LDO. Voltage regulator bypassed for VDD = 5V.VDD = 30V5V
IVDDVDD supply current. LDO mode (VDD > 7V)Operating, no audio signal25mA
Reset mode118µA
VDD supply current. LDO bypass mode (VDD = 5V)Operating, no audio signal150
Reset mode50
IAVDDGate-supply current. LDO bypass mode (VDD = 5V)Operating, no audio signal10mA
Reset mode1
IGVDDGate-supply current. LDO bypass mode (VDD = 5V), AD-mode modulation50% duty cycle16
Reset mode50µA
Gate-supply current. LDO bypass mode (VDD = 5V), HEAD-mode modulationHEAD-mode modulation16mA
Reset mode50µA
IPVDDTotal PVDD idle current, AD-mode modulation, BTL50% duty cycle with recommended output filter15mA
50% duty cycle with recommended output filter, TC = 25 °C13
Reset mode, No switching1
Total PVDD idle current, HEAD-mode modulation, BTLHEAD-mode modulation with recommended output filter10
HEAD-mode with recommended output filter, TC = 25 °C9
Reset mode, No switching1
ANALOG INPUTS
VINMaximum input voltage swing±2.8V
IINMaximum input current-11mA
GInverting voltage Gain, VOUT/VIN(Controller Mode)R1 = 5.6kΩ, R2 = OPEN18dB
R1 = 20kΩ, R2 = 100kΩ24
R1 = 39kΩ, R2 = 100kΩ30
R1 = 47kΩ, R2 = 75kΩ34
Inverting voltage Gain, VOUT/VIN(Peripheral Mode)R1 = 51kΩ, R2 = 51kΩ18
R1 = 75kΩ, R2 = 47kΩ24
R1 = 100kΩ, R2 = 39kΩ30
R1 = 100kΩ, R2 = 16kΩ34
RINInput resistanceG = 18dB48kΩ
G = 24dB24
G = 30dB12
G = 34dB7.7
OSCILLATOR
fOSC(IO)(1)Nominal, Controller ModeFPWM × 63.453.63.75MHz
AM1, Controller Mode3.063.1983.33
AM2, Controller Mode2.762.883
VIHHigh level input voltage1.88V
VILLow level input voltage1.65V
EXTERNAL OSCILLATOR (Peripheral Mode)
fOSC(IO)CLK input on OSCM/OSCP (Peripheral Mode)2.33.78MHz

OUTPUT-STAGE MOSFETs
RDS(on)Drain-to-source resistance, low side (LS)TJ = 25 °C, Excludes metallization resistance,
GVDD = 5V		70mΩ
Drain-to-source resistance, high side (HS)70mΩ
I/O PROTECTION
Vuvp,AVDDUndervoltage protection limit, AVDD4V
Vuvp,AVDD,hyst(2)Undervoltage protection hysteresis, AVDD0.1V
Vuvp,PVDD Undervoltage protection limit, PVDD_x 6.4 V
Vuvp,PVDD,hyst(2) Undervoltage protection hysteresis, PVDD_x 0.45 V
OTWOvertemperature warning, OTW_CLIP(2)115125135°C
OTWhyst(2)Temperature drop needed below OTW temperature for OTW_CLIP to be inactive after OTW event.20°C
OTE(2)Overtemperature error145155165°C
OTEhyst(2)A reset needs to occur for FAULT to be released following an OTE event20°C
OTE-OTW(differential)(2)OTE-OTW differential25°C
OLPCOverload protection counterfPWM = 600kHz (1024 PWM cycles)1.7ms
IOC, BTLOvercurrent limit protection, speaker output currentNominal peak current in 1Ω load10A
IOC, PBTL20A
IDCspkr, BTLDC Speaker Protection Current ThresholdBTL current imbalance threshold1.8A
IDCspkr, PBTLPBTL current imbalance threshold3.6A
IOCTOvercurrent response timeTime from switching transition to flip-state induced by overcurrent.150ns
IPDOutput pulldown current of each halfConnected when RESET is active to provide bootstrap charge. Not used in SE mode.3mA
STATIC DIGITAL SPECIFICATIONS
VIHHigh level input voltageHEAD, OSCM, OSCP, CMUTE, RESET1.9V
VILLow level input voltage0.8V
IlkgInput leakage current100μA
OTW/SHUTDOWN (FAULT)
RINT_PUInternal pullup resistance, OTW_CLIP to AVDD, FAULT to AVDD202632kΩ
VOHHigh level output voltageInternal pullup resistor33.33.6V
VOLLow level output voltageIO = 4mA200500mV
Device fanoutOTW_CLIP, FAULTNo external pullup30devices
(1) Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 4 : 4.5 : 5
(2) Specified by design.