SLASEE9C September   2017  – May 2025 TPA3221

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Characteristics (BTL)
    7. 6.7 Audio Characteristics (PBTL)
    8.     Typical Characteristics, BTL Configuration, AD-mode
    9.     Typical Characteristics, PBTL Configuration, AD-mode
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Internal LDO
        1. 8.3.1.1 Input Configuration, Gain Setting And Controller/Peripheral Operation
      2. 8.3.2 Gain Setting And Controller / Peripheral Operation
      3. 8.3.3 AD-Mode and HEAD-Mode PWM Modulation
      4. 8.3.4 Oscillator
      5. 8.3.5 Input Impedance
      6. 8.3.6 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Powering Up
        1. 8.4.1.1 Startup Ramp Time
      2. 8.4.2 Powering Down
        1. 8.4.2.1 Power Down Ramp Time
      3. 8.4.3 Device Reset
      4. 8.4.4 Device Soft Mute
      5. 8.4.5 Device Protection System
        1. 8.4.5.1 Overload and Short Circuit Current Protection
        2. 8.4.5.2 Signal Clipping and Pulse Injector
        3. 8.4.5.3 DC Speaker Protection
        4. 8.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.5.5 Overtemperature Protection OTW and OTE
        6. 8.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.5.7 Fault Handling
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 BST capacitors
          4. 9.2.1.2.4 PCB Material Recommendation
      2. 9.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
        1. 9.2.2.1 Design Requirements
      3. 9.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 9.2.3.1 Design Requirements
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
        1. 9.3.1.1 VDD Supply
        2. 9.3.1.2 AVDD and GVDD Supplies
        3. 9.3.1.3 PVDD Supply
        4. 9.3.1.4 BST Supply
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 BTL Application Printed Circuit Board Layout Example
        2. 9.4.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
        3. 9.4.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Gain Setting And Controller / Peripheral Operation

The gain of TPA3221 is set by the voltage divider connected to the GAIN/SLV control pin. Controller or Peripheral mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Controller mode in gains of 18, 24, 30, 34dB respectively, while the next four stages sets the GAIN in Peripheral mode in gains of 18, 24, 30, 34dB respectively. The gain setting is latched when RESET goes high and cannot be changed while RESET is high. Table 8-1 shows the recommended resistor values, the state and gain:

Table 8-1 Gain and Controller / Peripheral
Controller / Peripheral ModeGainR1 (to GND)R2 (to AVDD)Differential Input Signal Level
(each input pin)
Single Ended Input Signal Level
Controller18dB5.6kΩOPEN2VRMS2VRMS
Controller24dB20kΩ100kΩ1VRMS2VRMS
Controller30dB39kΩ100kΩ0.5VRMS1VRMS
Controller34dB47kΩ75kΩ0.32VRMS0.63VRMS
Peripheral18dB51kΩ51kΩ2VRMS2VRMS
Peripheral24dB75kΩ47kΩ1VRMS2VRMS
Peripheral30dB100kΩ39kΩ0.5VRMS1VRMS
Peripheral34dB100kΩ16kΩ0.32VRMS0.63VRMS
TPA3221 Gain and Controller / Peripheral SetupFigure 8-6 Gain and Controller / Peripheral Setup

For easy multi-channel system design TPA3221 has a Controller / Peripheral feature that allows automatic synchronization of multiple peripheral devices operated at the PWM switching frequency of a controller device. This benefits system noise performance by eliminating spurious crosstalk sum and difference tones due to unsynchronized channel-to-channel switching frequencies. Furthermore the Controller / Peripheral scheme is designed to interleave switching of the individual channels in a multi-channel system such that the power supply current ripple frequency is moved to a higher frequency which reduces the RMS ripple current in the power supply bulk capacitors.

The Controller / Peripheral scheme and the interleaving of the output stage switching is automatically configured by connecting the OSCx pins between a controller and multiple peripheral devices. Connect the OSCx pins in either positive or negative polarity to configure either a Peripheral1 or Peripheral2 device. Connect the OSCM of the Controller device to the OSCM of a peripheral device to configure for Peripheral1 or OSCP to configure for Peripheral2. Then connect the remaining OSCx pins between the controller and peripheral devices. The Controller, Peripheral1 and Peripheral2 PWM switching is be 30 degrees out of phase with each other. All switching channels are automatically synchronized by releasing RESET on all devices at the same time.

TPA3221 Gain and Controller PCB ImplementationFigure 8-7 Gain and Controller PCB Implementation

Placement on the PCB and connection of multiple TPA3221 devices in a multi channel system is illustrated in Figure 8-7. Peripheral devices should be placed on either side of the controller device, with a Peripheral1 device on one side of the Controller device, and a Peripheral2 device on the other. In systems with more than 3 TPA3221 devices, the controller should be in the middle, and every second peripheral devices should be a Peripheral1 or Peripheral 2 as illustrated in Figure 8-7. A 47kΩ pull up resistor to AVDD should be connected to the controller device OSCM output and a 47kΩ pull down resistor to GND should be connected to the controller OSCP CLK outputs.