SLASEE9C September   2017  – May 2025 TPA3221

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Characteristics (BTL)
    7. 6.7 Audio Characteristics (PBTL)
    8.     Typical Characteristics, BTL Configuration, AD-mode
    9.     Typical Characteristics, PBTL Configuration, AD-mode
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Internal LDO
        1. 8.3.1.1 Input Configuration, Gain Setting And Controller/Peripheral Operation
      2. 8.3.2 Gain Setting And Controller / Peripheral Operation
      3. 8.3.3 AD-Mode and HEAD-Mode PWM Modulation
      4. 8.3.4 Oscillator
      5. 8.3.5 Input Impedance
      6. 8.3.6 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Powering Up
        1. 8.4.1.1 Startup Ramp Time
      2. 8.4.2 Powering Down
        1. 8.4.2.1 Power Down Ramp Time
      3. 8.4.3 Device Reset
      4. 8.4.4 Device Soft Mute
      5. 8.4.5 Device Protection System
        1. 8.4.5.1 Overload and Short Circuit Current Protection
        2. 8.4.5.2 Signal Clipping and Pulse Injector
        3. 8.4.5.3 DC Speaker Protection
        4. 8.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.5.5 Overtemperature Protection OTW and OTE
        6. 8.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.5.7 Fault Handling
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 BST capacitors
          4. 9.2.1.2.4 PCB Material Recommendation
      2. 9.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
        1. 9.2.2.1 Design Requirements
      3. 9.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 9.2.3.1 Design Requirements
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supplies
        1. 9.3.1.1 VDD Supply
        2. 9.3.1.2 AVDD and GVDD Supplies
        3. 9.3.1.3 PVDD Supply
        4. 9.3.1.4 BST Supply
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
        1. 9.4.2.1 BTL Application Printed Circuit Board Layout Example
        2. 9.4.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
        3. 9.4.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.1.1 Design Requirements

For this design example, use the parameters in Table 9-1.

Table 9-1 Design Requirements, BTL Application
DESIGN PARAMETEREXAMPLE
Low Power Supply5 V
High Power Supply7 - 30 V
Analog InputsIN1_M = ±2.8V (peak, max)
IN1_P = ±2.8V (peak, max)
IN2_M = ±2.8V (peak, max)
IN2_P = ±2.8V (peak, max)
Output FiltersInductor-Capacitor Low Pass Filter (10 µH + 1 µF)
Speaker Impedance3 - 8 Ω