SLAU144K User guide

SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E

6.3 DMA Registers

Table 6-5 lists the memory-mapped registers for the DMA. All register offset addresses not listed in Table 6-5 should be considered as reserved locations and the register contents should not be modified.

Table 6-5 DMA Registers

Address	Acronym	Register Name	Type	Reset	Section
122h	DMACTL0	DMA control 0	Read/write	00h with POR	Section 6.4.1
124h	DMACTL1	DMA control 1	Read/write	00h with POR	Section 6.4.2
126h	DMAIV	DMA interrupt vector	Read/write	00h with POR	Section 6.4.7
1D0h	DMA0CTL	DMA channel 0 control	Read/write	00h with POR	Section 6.4.3
1D2h	DMA0SA	DMA channel 0 source address	Read/write	Unchanged	Section 6.4.4
1D6h	DMA0DA	DMA channel 0 destination address	Read/write	Unchanged	Section 6.4.5
1DAh	DMA0SZ	DMA channel 0 transfer size	Read/write	Unchanged	Section 6.4.6
1DCh	DMA1CTL	DMA channel 1 control	Read/write	00h with POR	Section 6.4.3
1DEh	DMA1SA	DMA channel 1 source address	Read/write	Unchanged	Section 6.4.4
1E2h	DMA1DA	DMA channel 1 destination address	Read/write	Unchanged	Section 6.4.5
1E6h	DMA1SZ	DMA channel 1 transfer size	Read/write	Unchanged	Section 6.4.6
1E8h	DMA2CTL	DMA channel 2 control	Read/write	00h with POR	Section 6.4.3
1EAh	DMA2SA	DMA channel 2 source address	Read/write	Unchanged	Section 6.4.4
1EEh	DMA1DA	DMA channel 2 destination address	Read/write	Unchanged	Section 6.4.5
1F2h	DMA2SZ	DMA channel 2 transfer size	Read/write	Unchanged	Section 6.4.6

6.4.1 DMACTL0 Register

DMA Control 0 Register

DMACTL0 is shown in Figure 6-6 and described in Table 6-6.

Return to Table 6-5.

Figure 6-6 DMACTL0 Register

15	14	13	12	11	10	9	8
Reserved				DMA2TSELx
rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)

7	6	5	4	3	2	1	0
DMA1TSELx				DMA0TSELx
rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)

Table 6-6 DMACTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	Reserved	R/W	0h
11-8	DMA2TSELx	R/W	0h	DMA trigger select. These bits select the DMA transfer trigger. 0000b = DMAREQ bit (software trigger) 0001b = TACCR2 CCIFG bit 0010b = TBCCR2 CCIFG bit 0011b = Serial data received UCA0RXIFG 0100b = Serial data transmit ready UCA0TXIFG 0101b = DAC12_0CTL DAC12IFG bit 0110b = ADC12 ADC12IFGx bit 0111b = TACCR0 CCIFG bit 1000b = TBCCR0 CCIFG bit 1001b = Serial data received UCA1RXIFG 1010b = Serial data transmit ready UCA1TXIFG 1011b = Multiplier ready 1100b = Serial data received UCB0RXIFG 1101b = Serial data transmit ready UCB0TXIFG 1110b = DMA0IFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111b = External trigger DMAE0
7-4	DMA1TSELx	R/W	0h	Same as DMA2TSELx
3-0	DMA0TSELx	R/W	0h	Same as DMA2TSELx

6.4.2 DMACTL1 Register

DMA Control 1 Register

DMACTL1 is shown in Figure 6-7 and described in Table 6-7.

Return to Table 6-5.

Figure 6-7 DMACTL1 Register

15	14	13	12	11	10	9	8
Reserved
r-0	r-0	r-0	r-0	r-0	r-0	r-0	r-0

7	6	5	4	3	2	1	0
Reserved					DMAONFETCH	ROUNDROBIN	ENNMI
r-0	r-0	r-0	r-0	r-0	rw-(0)	rw-(0)	rw-(0)

Table 6-7 DMACTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	Reserved	R	0h
2	DMAONFETCH	R/W	0h	DMA on fetch 0b = The DMA transfer occurs immediately. 1b = The DMA transfer occurs on next instruction fetch after the trigger.
1	ROUNDROBIN	R/W	0h	Round robin. This bit enables the round-robin DMA channel priorities. 0b = DMA channel priority is DMA0, DMA1, DMA2 1b = DMA channel priority changes with each transfer
0	ENNMI	R/W	0h	Enable NMI. This bit enables the interruption of a DMA transfer by an NMI interrupt. When an NMI interrupts a DMA transfer, the current transfer is completed normally, further transfers are stopped, and DMAABORT is set. 0b = NMI interrupt does not interrupt DMA transfer 1b = NMI interrupt interrupts a DMA transfer

6.4.3 DMAxCTL Register

DMA Channel x Control Register

DMAxCTL are shown in Figure 6-8 and described in Table 6-8.

Return to Table 6-5.

Figure 6-8 DMAxCTL Register

15	14	13	12	11	10	9	8
Reserved	DMADTx			DMADSTINCRx		DMASRCINCRx
rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)

7	6	5	4	3	2	1	0
DMADSTBYTE	DMASRCBYTE	DMALEVEL	DMAEN	DMAIFG	DMAIE	DMAABORT	DMAREQ
rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)	rw-(0)

Table 6-8 DMAxCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reserved	R/W	0h	Reserved
14-12	DMADTx	R/W	0h	DMA transfer mode 000b = Single transfer 001b = Block transfer 010b = Burst-block transfer 011b = Burst-block transfer 100b = Repeated single transfer 101b = Repeated block transfer 110b = Repeated burst-block transfer 111b = Repeated burst-block transfer
11-10	DMADSTINCRx	R/W	0h	DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer. When DMADSTBYTE = 1, the destination address increments or decrements by one. When DMADSTBYTE = 0, the destination address increments or decrements by two. The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented. DMAxDA is not incremented or decremented. 00b = Destination address is unchanged 01b = Destination address is unchanged 10b = Destination address is decremented 11b = Destination address is incremented
9-8	DMASRCINCRx	R/W	0h	DMA source increment. This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer. When DMASRCBYTE = 1, the source address increments or decrements by one. When DMASRCBYTE = 0, the source address increments or decrements by two. The DMAxSA is copied into a temporary register and the temporary register is incremented or decremented. DMAxSA is not incremented or decremented. 00b = Source address is unchanged 01b = Source address is unchanged 10b = Source address is decremented 11b = Source address is incremented
7	DMADSTBYTE	R/W	0h	DMA destination byte. This bit selects the destination as a byte or word. 0b = Word 1b = Byte
6	DMASRCBYTE	R/W	0h	DMA source byte. This bit selects the source as a byte or word. 0b = Word 1b = Byte
5	DMALEVEL	R/W	0h	DMA level. This bit selects between edge-sensitive and level-sensitive triggers. 0b = Edge sensitive (rising edge) 1b = Level sensitive (high level)
4	DMAEN	R/W	0h	DMA enable 0b = Disabled 1b = Enabled
3	DMAIFG	R/W	0h	DMA interrupt flag 0b = No interrupt pending 1b = Interrupt pending
2	DMAIE	R/W	0h	DMA interrupt enable 0b = Disabled 1b = Enabled
1	DMAABORT	R/W	0h	DMA abort. This bit indicates if a DMA transfer was interrupt by an NMI. 0b = DMA transfer not interrupted 1b = DMA transfer was interrupted by NMI
0	DMAREQ	R/W	0h	DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0b = No DMA start 1b = Start DMA

6.4.4 DMAxSA Register

DMA Channel x Source Address Register

DMAxSA is shown in Figure 6-9 and described in Table 6-9.

Return to Table 6-5.

Figure 6-9 DMAxSA Register

15	14	13	12	11	10	9	8
Reserved
r-0	r-0	r-0	r-0	r-0	r-0	r-0	r-0

7	6	5	4	3	2	1	0
Reserved				DMAxSA
r-0	r-0	r-0	r-0	rw	rw	rw	rw

15	14	13	12	11	10	9	8
DMAxSA
rw	rw	rw	rw	rw	rw	rw	rw

7	6	5	4	3	2	1	0
DMAxSA
rw	rw	rw	rw	rw	rw	rw	rw

Table 6-9 DMAxSA Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DMAxSA	R/W	Unchanged	DMA source address The source address register points to the DMA source address for single transfers or the first source address for block transfers. The source address register remains unchanged during block and burst-block transfers. Devices that have addressable memory range 64KB or less contain a single word for the DMAxSA. The upper word is automatically cleared when writing using word operations. Reads from this location are always read as zero. Devices that have addressable memory range that is more than 64KB contain an additional word for the source address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxSA with word formats, this additional word is automatically cleared. Reads of this additional word using word formats are always read as zero.

Bit

Field

Type

Reset

Description

15-0

DMAxSA

R/W

Unchanged

DMA source address

The source address register points to the DMA source address for single transfers or the first source address for block transfers. The source address register remains unchanged during block and burst-block transfers.

Devices that have addressable memory range 64KB or less contain a single word for the DMAxSA. The upper word is automatically cleared when writing using word operations. Reads from this location are always read as zero.

Devices that have addressable memory range that is more than 64KB contain an additional word for the source address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxSA with word formats, this additional word is automatically cleared. Reads of this additional word using word formats are always read as zero.

6.4.5 DMAxDA Register

DMA Channel x Destination Address Register

DMAxDA is shown in Figure 6-10 and described in Table 6-10.

Return to Table 6-5.

Figure 6-10 DMAxDA Register

15	14	13	12	11	10	9	8
Reserved
r-0	r-0	r-0	r-0	r-0	r-0	r-0	r-0

7	6	5	4	3	2	1	0
Reserved				DMAxDA
r-0	r-0	r-0	r-0	rw	rw	rw	rw

15	14	13	12	11	10	9	8
DMAxDA
rw	rw	rw	rw	rw	rw	rw	rw

7	6	5	4	3	2	1	0
DMAxDA
rw	rw	rw	rw	rw	rw	rw	rw

Table 6-10 DMAxDA Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DMAxDA	R/W	Unchanged	DMA destination address The destination address register points to the DMA destination address for single transfers or the first destination address for block transfers. The destination address register remains unchanged during block and burst-block transfers. Devices that have addressable memory range 64KB or less contain a single word for the DMAxDA. Devices that have addressable memory range that is more than 64KB contain an additional word for the destination address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxDA with word formats, this additional word is automatically cleared. Reads of this additional word using word formats are always read as zero.

Bit

Field

Type

Reset

Description

15-0

DMAxDA

R/W

Unchanged

DMA destination address

The destination address register points to the DMA destination address for single transfers or the first destination address for block transfers. The destination address register remains unchanged during block and burst-block transfers.

Devices that have addressable memory range 64KB or less contain a single word for the DMAxDA.

Devices that have addressable memory range that is more than 64KB contain an additional word for the destination address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxDA with word formats, this additional word is automatically cleared. Reads of this additional word using word formats are always read as zero.

6.4.6 DMAxSZ Register

DMA Channel x Size Register

DMAxSZ is shown in Figure 6-11 and described in Table 6-11.

Return to Table 6-5.

Figure 6-11 DMAxSZ Register

15	14	13	12	11	10	9	8
DMAxSZ
rw	rw	rw	rw	rw	rw	rw	rw

7	6	5	4	3	2	1	0
DMAxSZ
rw	rw	rw	rw	rw	rw	rw	rw

Table 6-11 DMAxSZ Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DMAxSZ	R/W	Unchanged	DMA size. The DMA size register defines the number of byte/word data per block transfer. DMAxSZ register decrements with each word or byte transfer. When DMAxSZ decrements to 0, it is immediately and automatically reloaded with its previously initialized value. 00000h = Transfer is disabled 00001h = 1 byte or word to be transferred 00002h = 2 bytes or words have to be transferred ⋮ 0FFFFh = 65535 bytes or words have to be transferred

Bit

Field

Type

Reset

Description

15-0

DMAxSZ

R/W

Unchanged

DMA size. The DMA size register defines the number of byte/word data per block transfer. DMAxSZ register decrements with each word or byte transfer. When DMAxSZ decrements to 0, it is immediately and automatically reloaded with its previously initialized value.

00000h = Transfer is disabled

00001h = 1 byte or word to be transferred

00002h = 2 bytes or words have to be transferred

⋮

0FFFFh = 65535 bytes or words have to be transferred

6.4.7 DMAIV Register

DMA Interrupt Vector Register

DMAIV is shown in Figure 6-12 and described in Table 6-12.

Return to Table 6-5.

Figure 6-12 DMAIV Register

15	14	13	12	11	10	9	8
DMAIVx
r-0	r-0	r-0	r-0	r-0	r-0	r-0	r-0

7	6	5	4	3	2	1	0
DMAIVx
r-0	r-0	r-0	r-0	r-(0)	r-(0)	r-(0)	r-0

Table 6-12 DMAIV Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DMAIVx	R	0h	DMA interrupt vector value. See Table 6-13.

Table 6-13 DMA Interrupt Vector Values

DMAIV Contents	Interrupt Source	Interrupt Flag	Interrupt Priority
00h	No interrupt pending	–
02h	DMA channel 0	DMA0IFG	Highest
04h	DMA channel 1	DMA1IFG
06h	DMA channel 2	DMA2IFG
08h	Reserved	–
0Ah	Reserved	–
0Ch	Reserved	–
0Eh	Reserved	–	Lowest