SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 21-1 lists the memory-mapped registers for the Comparator_A+.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
59h | CACTL1 | Comparator_A+ control 1 | Read/write | 00h with POR | Section 21.4.1 |
5Ah | CACTL2 | Comparator_A+ control 2 | Read/write | 00h with POR | Section 21.4.2 |
5Bh | CAPD | Comparator_A+ port disable | Read/write | 00h with POR | Section 21.4.3 |
Comparator_A+ Control 1 Register
CACTL1 is shown in Figure 21-8 and described in Table 21-2.
Return to Table 21-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAEX | CARSEL | CAREFx | CAON | CAIES | CAIE | CAIFG | |
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CAEX | R/W | 0h | Comparator_A+ exchange. This bit exchanges the comparator inputs and inverts the comparator output. |
6 | CARSEL | R/W | 0h | Comparator_A+ reference select. This bit selects which terminal the VCAREF is applied to. When CAEX = 0: 0b = VCAREF is applied to the positive terminal 01b = VCAREF is applied to the negative terminal When CAEX = 1: 0b = VCAREF is applied to the negative terminal 1b = VCAREF is applied to the positive terminal |
5-4 | CAREF | R/W | 0h | Comparator_A+ reference. These bits select the reference voltage VCAREF. 00b = Internal reference off. An external reference can be applied. 01b = 0.25 × VCC 10b = 0.50 × VCC 11b = Diode reference is selected |
3 | CAON | R/W | 0h | Comparator_A+ on. This bit turns on the comparator. When the comparator is off it consumes no current. The reference circuitry is enabled or disabled independently. 0b = Off 1b = On |
2 | CAIES | R/W | 0h | Comparator_A+ interrupt edge select 0b = Rising edge 1b = Falling edge |
1 | CAIE | R/W | 0h | Comparator_A+ interrupt enable 0b = Disabled 1b = Enabled |
0 | CAIFG | R/W | 0h | The Comparator_A+ interrupt flag 0b = No interrupt pending 1b = Interrupt pending |
Comparator_A+ Control Register 2 Register
CACTL2 is shown in Figure 21-9 and described in Table 21-3.
Return to Table 21-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CASHORT | P2CA4 | P2CA3 | P2CA2 | P2CA1 | P2CA0 | CAF | CAOUT |
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | r-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CASHORT | R/W | 0h | Input short. This bit shorts the positive and negative input terminals. 0b = Inputs not shorted 1b = Inputs shorted |
6 | P2CA4 | R/W | 0h | Input select. This bit together with P2CA0 selects the positive terminal input when CAEX = 0 and the negative terminal input when CAEX = 1. |
5 | P2CA3 | R/W | 0h | Input select. These bits select the negative terminal input when CAEX = 0 and the positive terminal input when CAEX = 1. MSP430G2210: Only channels 2, 5, 6, and 7 are available. Other channels should not be selected. 000b = No connection 001b = CA1 010b = CA2 011b = CA3 100b = CA4 101b = CA5 110b = CA6 111b = CA7 |
4 | P2CA2 | R/W | 0h | |
3 | P2CA1 | R/W | 0h | |
2 | P2CA0 | R/W | 0h | Input select. This bit, together with P2CA4, selects the positive terminal input when CAEX = 0 and the negative terminal input when CAEX = 1. 00b = No connection 01b = CA0 10b = CA1 11b = CA2 |
1 | CAF | R/W | 0h | Comparator_A+ output filter 0b = Comparator_A+ output is not filtered 1b = Comparator_A+ output is filtered |
0 | CAOUT | R | 0h | Comparator_A+ output. This bit reflects the value of the comparator output. Writing this bit has no effect. |
Comparator_A+ Port Disable Register
CAPD is shown in Figure 21-10 and described in Table 21-4.
Return to Table 21-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPD7 | CAPD6 | CAPD5 | CAPD4 | CAPD3 | CAPD2 | CAPD1 | CAPD0 |
rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CAPDx#SLAU144CAP9254 | R/W | 0h | Comparator_A+ port disable. These bits individually disable the input buffer for the pins of the port associated with Comparator_A+. For example, if CA0 is on pin P2.3, the CAPDx bits can be used to individually enable or disable each P2.x pin buffer. CAPD0 disables P2.0, CAPD1 disables P2.1, and so forth. 0b = The input buffer is enabled. 1b = The input buffer is disabled. |