SLAU858B December   2023  – June 2025 AFE881H1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
  6. 2Hardware
    1. 2.1 Hardware Description
      1. 2.1.1 Theory of Operation
      2. 2.1.2 Signal Definitions
    2. 2.2 Hardware Setup
      1. 2.2.1 Electrostatic Discharge Caution
      2. 2.2.2 Power Configuration and Jumper Settings
      3. 2.2.3 Connecting the Hardware
        1. 2.2.3.1 Power Configuration
        2. 2.2.3.2 External SPI and UART Controllers
  7. 3Software
    1. 3.1 Software Setup
    2. 3.2 Software Description
      1. 3.2.1 Starting the Software
      2. 3.2.2 Software Features
        1. 3.2.2.1 High Level Configuration Page
        2. 3.2.2.2 AFE881H1 Register Page
  8. 4Hardware Design Files
    1. 4.1 Board Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Related Documentation
  11. 7Revision History

2.1.2 Signal Definitions

The EVM board provides access to the digital AFE881H1 pins through headers J6 and J12. Table 2-1 lists the J6 pin definitions and Table 2-2 lists the J12 pin definitions.

Table 2-1 AFE881H1 Header J6 Pin Definitions
Pin Number Signal Description
1 SCLK AFE881H1 SPI serial clock input
3 PICO AFE881H1 SDI (serial data input)
5 POCI AFE881H1 SDO (serial data output)
7 CS AFE881H1 chip select input
9 TXD AFE881H1 UART output
11 RXD AFE881H1 UART input
13 RTS AFE881H1 HART request to send
2, 4, 6, 8, 10, 12, 14 GND Ground
Table 2-2 AFE881H1 Header J12 Pin Definitions
Pin Number Signal Description
1 CD AFE881H1 HART carrier detect
3 RESET AFE881H1 device reset
5 ALARM AFE881H1 alarm signal
2, 4, 6 GND Ground