SLAU858B December 2023 – June 2025 AFE881H1
Figure 2-1 shows the block diagram of the AFE881H1EVM board. The AFE881H1 connects to a local machine USB port through a USB-A to Micro-USB cable.
With the default jumper settings, the USB sources a 3.3V supply for PVDD and a 1.8V supply for IOVDD. The PVDD and IOVDD supplies can source on-board power through J21 and J20, respectively. VDD can also be selected using J21. To use external supplies, remove the shunts connecting the jumpers and use the banana jack connectors at J15 for PVDD, J17 for IOVDD, and J18 for VDD.
SMA connector J11 is coupled to the HART input of the AFE881H1. Jumpers at J2 and J4 determine if the HART signal is capacitively coupled to the device, or if the HART signal connects to the device through an external filter. Access the HART output at SMA connector J14. SMA connectors J7 and J10 connect to the inputs of a 16-bit ADC on the AFE881H1, and SMA connector J13 connects to the device CLK_OUT output clock. Additionally, SMA connector J8 is available for the VOUT of the AFE881H1.