SLAU957 June   2025 TRF1108 , TRF1208

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Interfaces
  9. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
      1. 3.2.1 HSDC Pro Overview
      2. 3.2.2 Latte Overview
        1. 3.2.2.1 Latte Shortcuts
  10. 4Implementation Results
    1. 4.1 Evaluation Setup TRF-LSC-AFE7950EVM Automatic Configuration
      1. 4.1.1 Recommended Test Environment
      2. 4.1.2 Required Hardware
      3. 4.1.3 Steps to Start Automatic Configuration
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
      6. 4.1.6 TRF-LSC-AFE7950EVM Manual Configuration
        1. 4.1.6.1 TSW14J5x DAC Pattern Setup
        2. 4.1.6.2 Connect Latte to Board
        3. 4.1.6.3 Compile Libraries
        4. 4.1.6.4 Program TRF-LSC-AFE7950EVM
        5. 4.1.6.5 Modify Configuration
      7. 4.1.7 Setup the TSW14J5x With the HSDC PRO
        1. 4.1.7.1 DAC Pattern Setup and Send
        2. 4.1.7.2 DAC Synchronization Check
        3. 4.1.7.3 ADC Data Capture
        4. 4.1.7.4 ADC Synchronization Check
    2. 4.2 Status Check and Troubleshooting Guidelines
      1. 4.2.1 EVM Status Indicators
      2. 4.2.2 TSW14J56 EVM
    3. 4.3 Performance Data and Results
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks

4.1.7.3 ADC Data Capture

The steps to capture the ADC output are as follows:

  1. Click on the HSDC PRO ADC tab. Figure 4-14 shows a brief description of the ADC tab.
    TRF-LSC-AFE7950EVM HSDC PRO ADC Tab Overview Figure 4-14 HSDC PRO ADC Tab Overview
  2. Select AFE79xx_2x2RX_24410 as the device.
  3. Go to Data Capture Options in the menu bar and choose the Capture option. Set samples (per channel) to 16384. Click the OK button.
  4. Select 16384 in the Analysis window located in the lower-left section of the GUI.
  5. Enter 245.76 M for ADC output data rate.
  6. Click the Capture button.

The capture size is set to a lower value (such as 16K) because of the limited BRAM memory available in the FPGA.