SLAU957 June   2025 TRF1108 , TRF1208

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Interfaces
  9. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
      1. 3.2.1 HSDC Pro Overview
      2. 3.2.2 Latte Overview
        1. 3.2.2.1 Latte Shortcuts
  10. 4Implementation Results
    1. 4.1 Evaluation Setup TRF-LSC-AFE7950EVM Automatic Configuration
      1. 4.1.1 Recommended Test Environment
      2. 4.1.2 Required Hardware
      3. 4.1.3 Steps to Start Automatic Configuration
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
      6. 4.1.6 TRF-LSC-AFE7950EVM Manual Configuration
        1. 4.1.6.1 TSW14J5x DAC Pattern Setup
        2. 4.1.6.2 Connect Latte to Board
        3. 4.1.6.3 Compile Libraries
        4. 4.1.6.4 Program TRF-LSC-AFE7950EVM
        5. 4.1.6.5 Modify Configuration
      7. 4.1.7 Setup the TSW14J5x With the HSDC PRO
        1. 4.1.7.1 DAC Pattern Setup and Send
        2. 4.1.7.2 DAC Synchronization Check
        3. 4.1.7.3 ADC Data Capture
        4. 4.1.7.4 ADC Synchronization Check
    2. 4.2 Status Check and Troubleshooting Guidelines
      1. 4.2.1 EVM Status Indicators
      2. 4.2.2 TSW14J56 EVM
    3. 4.3 Performance Data and Results
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks

4.2.1 EVM Status Indicators

At this point, green LED D3 is lit. D3 indicates that PLL loop 2 of the TRF-LSC-AFE7950EVM is locked. Optionally, LED D4 indicates that PLL loop 1 of the TRF-LSC-AFE7950EVM is locked. If there are external equipment providing a 10MHz reference to the TRF-LSC-AFE7950EVM for lab-equipment synchronization, then LED D4 is lit. The EVM still functions without PLL loop 1 running, but PLL loop 2 is necessary for a successful bringup.

  • If PLL loop 1 is not running, then check the 10MHz reference. This check is necessary to achieve signal coherency with the signal generators and spectrum analyzer.
  • If PLL loop 2 is not locked, then contact TI applications for additional support.