Description

When the SSI is configured in Bi- or Quad-mode, and a read from external memory is performed after the SSI is configured for Receive Mode, bus contention can occur on the SSI data pins on that first data read.

Workaround

Perform a dummy read from memory before the first valid read operation after configuring the SSI for Receive Mode (setting the DIR bit in the QSSI Control (SSICR1) register). For example:

    SSIConfigSetExpClk(SSI0_BASE,SysCtlClockFreqSet (), 
    SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
    SSIAdvModeSet(SSI0_BASE, SSI_ADV_BI_READ); //Receive Mode set
    SSIDataPut(SSI0_BASE, &pui32DataRx[ui32Index]); //intentional dummy write
    SSIDataGetNonBlocking(SSI-_BASE, ui32Dummy); //dummy read
    SSIDataPut(SSI0_BASE, &pui32DataRx[ui32Index]); //intentional dummy write
    SSIDataGetNonBlocking(SSI0_BASE, &pui32DataRx[0])); //first intentional read
    SSIDataPut(SSI0_BASE, &pui32DataRx[ui32Index]); //intentional dummy write
    SSIDataGetNonBlocking(SSI0_BASE, &pui32DataRx[1])); //second intentional read

If the transfer normally requires any dummy operations, such as the intentional dummy writes shown above, the dummy read should occur before the normal dummy operations.

Note that if your application is sensitive to the SSIClk, the dummy read outputs a clock cycle. Reconfigure the SSIClk pin to a GPIO input while performing the dummy read to prevent this from affecting your clock-sensitive application.