SLAZ709A October 2017 – June 2025 MSP432E401Y , MSP432E411Y
Table 1-1 lists the device errata.
| Name | Errata Title |
|---|---|
| ADC | |
| ADC#13 | A glitch can occur on pin PE3 when using any ADC analog input channel to sample |
| ADC#14 | The first two ADC samples may be incorrect |
| EPI | |
| EPI#01 | Data reads can be corrupted when the code address space in the EPI module is used |
| GPIO | |
| GPIO#09 | In some cases, noise injected into GPIO pins PB0 and PB1 can cause high current draw |
| General-Purpose Timers | |
| GPTM#09 | General-purpose timers do not synchronize when configured for RTC mode |
| GPTM#15 | Counter does not immediately clear to 0 when MATCH is reached in edge count up mode |
| Hibernation | |
| HIB#10 | If MEMCLR is set to a nonzero value, a tamper event may not clear all of the bits in the HIBDATA register |
| HIB#16 | Application code may miss new tamper event during clear |
| HIB#18 | Can get two matches per day in calendar mode |
| HIB#19 | The first write to the HIBCTL register may not complete successfully after a Hibernation module reset |
| Memory | |
| MEM#07 | Soft resets should not be asserted during EEPROM operations |
| MEM#15 | Specific flash locations in any sector do not get erased |
| MEM#16 | JTAG unlock issue when BOOTCFG is committed with NW=0 |
| PWM | |
| PWM#04 | PWM generator interrupts can only be cleared 1 PWM clock cycle after the interrupt occurs |
| PWM#05 | Generator load with global sync may lead to erroneous pulse width |
| PWM#06 | PWM output may generate a continuous high instead of a low or a continuous low instead of high |
| QEI | |
| QEI#01 | When using the index pulse to reset the counter, a specific initial condition in the QEI module causes the direction for the first count to be misread |
| SSI | |
| SSI#03 | SSI1 can only be used in legacy mode |
| SSI#05 | Bus contention in bi- and quad-mode of SSI |
| SSI#06 | SSI receive FIFO time-out interrupt may assert sooner than expected in slave mode |
| SSI#07 | SSI transmit interrupt status bit is not latched |
| SSI#08 | SSI slave in bi and quad mode swaps XDAT0 and XDAT1 |
| System Control | |
| SYSCTL#03 | The MOSC verification circuit does not detect a loss of clock after the clock has been successfully operating |
| SYSCTL#18 | DIVSCLK outputs a different clock frequency than expected when DIV = 0x0 |
| SYSCTL#24 | Modules may not be ready for access if their power domains are first turned off and then on |
| USB | |
| USB#04 | Device sends SE0 in response to a USB bus reset |
| Watchdog Timers | |
| WDT#08 | Reading the WDTVALUE register may return incorrect values when using Watchdog Timer 1 |