Description

In the Divisor and Source Clock Configuration (DIVSCLK) register, if the DIV bit field is 0x0 (divided by 1), the clock output to the GPIO is not what is expected:

• If the DIV bit field has not yet been adjusted in code, the clock frequency will be the clock source defined in the SRC bit field divided by 32. For example, if SRC = 0x1 (PIOSC) and DIV = 0x0, the clock output to the GPIO will have a frequency of 500 kHz, derived from the PIOSC.
• If the DIV bit field has already been adjusted in code, the clock frequency will be the clock source defined in the SRC bit field divided by the previous DIV bit field value. For example, if SRC = 0x1 (PIOSC) and DIV was previously 0x1 (divided by 2) then written to 0x0, the clock output to the GPIO will have a frequency of 8 MHz, derived from the PIOSC.

Workaround

If clock accuracy of the source is not a factor, certain frequencies can be achieved using a non-zero DIV value and a different SRC value. For example, to achieve a 16 MHz clock, instead of SRC = 0x1 (PIOSC) and DIV = 0x0, use SRC = 0x0 (System Clock) and the respective DIV value (DIV = 0x4 (divided by 5) for a system clock of 80 MHz).