SLDS216B December   2017  – February 2025 PGA302

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Overvoltage and Reverse Voltage Protection
    6. 5.6  Linear Regulators
    7. 5.7  Internal Reference
    8. 5.8  Internal Oscillator
    9. 5.9  Bridge Sensor Supply
    10. 5.10 Temperature Sensor Supply
    11. 5.11 Bridge Offset Cancel
    12. 5.12 P Gain and T Gain Input Amplifiers (Chopper Stabilized)
    13. 5.13 Analog-to-Digital Converter
    14. 5.14 Internal Temperature Sensor
    15. 5.15 Bridge Current Measurement
    16. 5.16 One Wire Interface
    17. 5.17 DAC Output
    18. 5.18 DAC Gain for DAC Output
    19. 5.19 Non-Volatile Memory
    20. 5.20 Diagnostics - PGA30x
    21. 5.21 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Overvoltage and Reverse Voltage Protection
      2. 6.3.2  Linear Regulators
      3. 6.3.3  Internal Reference
      4. 6.3.4  Internal Oscillator
      5. 6.3.5  VBRGP and VBRGN Supply for Resistive Bridge
      6. 6.3.6  ITEMP Supply for Temperature Sensor
      7. 6.3.7  P Gain
      8. 6.3.8  T Gain
      9. 6.3.9  Bridge Offset Cancel
      10. 6.3.10 Analog-to-Digital Converter
        1. 6.3.10.1 Sigma Delta Modulator for ADC
        2. 6.3.10.2 Decimation Filter for ADC
        3. 6.3.10.3 Internal Temperature Sensor ADC Conversion
        4. 6.3.10.4 ADC Scan Mode
          1. 6.3.10.4.1 P-T Multiplexer Timing in Auto Scan Mode
      11. 6.3.11 Internal Temperature Sensor
      12. 6.3.12 Bridge Current Measurement
      13. 6.3.13 Digital Interface
      14. 6.3.14 OWI
        1. 6.3.14.1 Overview of OWI Interface
        2. 6.3.14.2 Activating and Deactivating the OWI Interface
          1. 6.3.14.2.1 Activating OWI Communication
          2. 6.3.14.2.2 Deactivating OWI Communication
        3. 6.3.14.3 OWI Protocol
          1. 6.3.14.3.1 OWI Frame Structure
            1. 6.3.14.3.1.1 Standard field structure:
            2. 6.3.14.3.1.2 Frame Structure
            3. 6.3.14.3.1.3 Sync Field
            4. 6.3.14.3.1.4 Command Field
            5. 6.3.14.3.1.5 Data Field(s)
          2. 6.3.14.3.2 OWI Commands
            1. 6.3.14.3.2.1 OWI Write Command
            2. 6.3.14.3.2.2 OWI Read Initialization Command
            3. 6.3.14.3.2.3 OWI Read Response Command
            4. 6.3.14.3.2.4 OWI Burst Write Command (EEPROM Cache Access)
            5. 6.3.14.3.2.5 OWI Burst Read Command (EEPROM Cache Access)
          3. 6.3.14.3.3 OWI Operations
            1. 6.3.14.3.3.1 Write Operation
            2. 6.3.14.3.3.2 Read Operation
            3. 6.3.14.3.3.3 EEPROM Burst Write
            4. 6.3.14.3.3.4 EEPROM Burst Read
        4. 6.3.14.4 OWI Communication Error Status
      15. 6.3.15 I2C Interface
        1. 6.3.15.1 Overview of I2C Interface
        2. 6.3.15.2 I2C Interface Protocol
        3. 6.3.15.3 Clocking Details of I2C Interface
      16. 6.3.16 DAC Output
      17. 6.3.17 DAC Gain for DAC Output
        1. 6.3.17.1 Connecting DAC Output to DAC GAIN Input
      18. 6.3.18 Memory
        1. 6.3.18.1 EEPROM Memory
          1. 6.3.18.1.1 EEPROM Cache
          2. 6.3.18.1.2 EEPROM Programming Procedure
          3. 6.3.18.1.3 EEPROM Programming Current
          4. 6.3.18.1.4 CRC
      19. 6.3.19 Diagnostics
        1. 6.3.19.1 Power Supply Diagnostics
        2. 6.3.19.2 Sensor Connectivity/Gain Input Faults
        3. 6.3.19.3 Gain Output Diagnostics
        4. 6.3.19.4 PGA302 Harness Open Wire Diagnostics
        5. 6.3.19.5 EEPROM CRC and TRIM Error
      20. 6.3.20 Digital Compensation and Filter
        1. 6.3.20.1 Digital Gain and Offset
        2. 6.3.20.2 TC and NL Correction
        3. 6.3.20.3 Clamping
        4. 6.3.20.4 Filter
      21. 6.3.21 Revision ID
    4. 6.4 Device Functional Modes
  8. 7 Register Maps
    1. 7.1 Programmer's Model
      1. 7.1.1 Memory Map
      2. 7.1.2 Control and Status Registers
        1. 7.1.2.1  MICRO_INTERFACE_CONTROL (DI Page Address = 0x0) (DI Page Offset = 0x0C)
        2. 7.1.2.2  PSMON1 (M0 Address= 0x40000558) (DI Page Address = 0x2) (DI Page Offset = 0x58)
        3. 7.1.2.3  AFEDIAG (M0 Address= 0x4000055A) (DI Page Address = 0x2) (DI Page Offset = 0x5A)
        4. 7.1.2.4  P_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x47)
        5. 7.1.2.5  T_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x48)
        6. 7.1.2.6  TEMP_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x4C)
        7. 7.1.2.7  OFFSET_CANCEL (DI Page Address = 0x2) (DI Page Offset = 0x4E)
        8. 7.1.2.8  PADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x10)
        9. 7.1.2.9  PADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x11)
        10. 7.1.2.10 TADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x14)
        11. 7.1.2.11 TADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x15)
        12. 7.1.2.12 DAC_REG0_1 (DI Page Address = 0x2) (DI Page Offset = 0x30)
        13. 7.1.2.13 DAC_REG0_2 (DI Page Address = 0x2) (DI Page Offset = 0x31)
        14. 7.1.2.14 OP_STAGE_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x3B)
        15. 7.1.2.15 EEPROM_ARRAY (DI Page Address = 0x5) (DI Page Offset = 0x00 - 0x7F)
        16. 7.1.2.16 EEPROM_CACHE_BYTE0 (DI Page Address = 0x5) (DI Page Offset = 0x80)
        17. 7.1.2.17 EEPROM_CACHE_BYTE1 (DI Page Address = 0x5) (DI Page Offset = 0x81)
        18. 7.1.2.18 EEPROM_PAGE_ADDRESS (DI Page Address = 0x5) (DI Page Offset = 0x82)
        19. 7.1.2.19 EEPROM_CTRL (DI Page Address = 0x5) (DI Page Offset = 0x83)
        20. 7.1.2.20 EEPROM_CRC (DI Page Address = 0x5) (DI Page Offset = 0x84)
        21. 7.1.2.21 EEPROM_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x85)
        22. 7.1.2.22 EEPROM_CRC_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x86)
        23. 7.1.2.23 EEPROM_CRC_VALUE (DI Page Address = 0x5) (DI Page Offset = 0x87)
        24. 7.1.2.24 H0 (EEPROM Address= 0x40000000)
        25. 7.1.2.25 H1 (EEPROM Address= 0x40000002)
        26. 7.1.2.26 H2 (EEPROM Address= 0x40000004)
        27. 7.1.2.27 H3 (EEPROM Address= 0x40000006)
        28. 7.1.2.28 G0 (EEPROM Address= 0x40000008)
        29. 7.1.2.29 G1 (EEPROM Address= 0x4000000A)
        30. 7.1.2.30 G2 (EEPROM Address= 0x4000000C)
        31. 7.1.2.31 G3 (EEPROM Address= 0x4000000E)
        32. 7.1.2.32 N0 (EEPROM Address= 0x40000010)
        33. 7.1.2.33 N1 (EEPROM Address= 0x40000012)
        34. 7.1.2.34 N2 (EEPROM Address= 0x40000014)
        35. 7.1.2.35 N3 (EEPROM Address= 0x40000016)
        36. 7.1.2.36 M0 (EEPROM Address= 0x40000018)
        37. 7.1.2.37 M1 (EEPROM Address= 0x4000001A)
        38. 7.1.2.38 M2 (EEPROM Address= 0x4000001C)
        39. 7.1.2.39 M3 (EEPROM Address= 0x4000001E)
        40. 7.1.2.40 PADC_GAIN (EEPROM Address= 0x40000020)
        41. 7.1.2.41 TADC_GAIN (EEPROM Address= 0x40000021)
        42. 7.1.2.42 PADC_OFFSET (EEPROM Address= 0x40000022)
        43. 7.1.2.43 TADC_OFFSET (EEPROM Address= 0x40000024)
        44. 7.1.2.44 TEMP_SW_CTRL (EEPROM Address= 0x40000028)
        45. 7.1.2.45 DAC_FAULT_MSB (EEPROM Address= 0x4000002A)
        46. 7.1.2.46 LPF_A0_MSB (EEPROM Address= 0x4000002B)
        47. 7.1.2.47 LPF_A1 (EEPROM Address= 0x4000002C)
        48. 7.1.2.48 LPF_A2 (EEPROM Address= 0x4000002E)
        49. 7.1.2.49 .LPF_B1 (EEPROM Address= 0x40000030)
        50. 7.1.2.50 NORMAL_LOW (EEPROM Address= 0x40000032)
        51. 7.1.2.51 NORMAL_HIGH (EEPROM Address= 0x40000034)
        52. 7.1.2.52 LOW_CLAMP (EEPROM Address= 0x40000036)
        53. 7.1.2.53 HIGH_CLAMP (EEPROM Address= 0x40000038)
        54. 7.1.2.54 DIAG_BIT_EN (EEPROM Address= 0x4000003A)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 0-5V Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Data
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.15.2 I2C Interface Protocol

The basic Protocol of the I2C frame for a Write operation is shown in Figure 6-17:

PGA302 I2C Write Operation: A Controller-Transmitter Addressing a PGA302 Target With a 7-Bit Target AddressFigure 6-17 I2C Write Operation: A Controller-Transmitter Addressing a PGA302 Target With a 7-Bit Target Address

The diagram represents the data fed into or out from the I2C SDA port.

The basic data transfer is to send 2 bytes of data to the specified Target Address. The first data field is the register address and the second data field is the data sent or received.

The I2C Target Address is used to determine which memory page is being referenced. Table 6-5 shows the mapping of the target address to the memory page.

Table 6-5 Target Addresses
Target Address PGA302 Memory Page
0x40 Test Registers
0x42 Control and Status Registers, DI_PAGE_ADDRESS = 0x02
0x45 EEPROM Cache/Cells
0x46 Reserved
0x47 Control and Status Registers, DI_PAGE_ADDRESS = 0x07

The basic PGA302 I2C Protocol for a read operation is shown in Figure 6-18.

PGA302 I2C Read Operation: A Controller-Transmitter Addressing a PGA302 Target With a 7-Bit Target AddressFigure 6-18 I2C Read Operation: A Controller-Transmitter Addressing a PGA302 Target With a 7-Bit Target Address

The Target Address determines the memory page. The R/W bit is set to 0.

The Register Address specifies the 8-bit address of the requested data.

The Repeat Start Condition replaces the write data from the above write operation description. This informs the PGA302 devices that Read operation will take place instead of a write operation.

The second Target Address contains the memory page from which the data will be retrieved. The R/W bit is set to 1.

Target data is transmitted after the acknowledge is received by the controller.

Table 6-6 lists a few examples of I2C Transfers.

Table 6-6 I2C Transfers Examples
Command Controller to Target Data on I2C SDA
Read COM_MCU_TO_DIF_B0

Target Address: 100 0000

Register Address: 0000 0100
Write 0x80 to Control and Status Registers 0x30 (DAC_REG0_1)

Target Address: 100 0010

Register Address: 0011 0000

Data: 1000 0000
Read from EEPROM Byte 7

Target Address: 100 0101

Register Address: 0000 0111