SLLA383A February   2018  – August 2022 SN65HVDA100-Q1 , SN65HVDA195-Q1 , TLIN1022-Q1 , TLIN1029-Q1 , TLIN2022-Q1 , TLIN2029-Q1 , TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 LIN Specification Progression
    2. 1.2 Workflow Concept
  4. 2Network Architecture
    1. 2.1 General Layout of the LIN Bus
    2. 2.2 Serial Communication Principles
    3. 2.3 Commander-Responder Principle
    4. 2.4 Message Frame Format
  5. 3Physical Layer Requirements
    1. 3.1 Bus Signaling Fundamentals
    2. 3.2 Pullup Values
    3. 3.3 Threshold Values
    4. 3.4 Bit-Rate Tolerance and Timing Requirements
    5. 3.5 Synchronization and Bit Sampling
    6. 3.6 Duty Cycle
  6. 4Filtering, Distance Limitations, Nodes on Bus
    1. 4.1 EMI and Signal Conditioning
    2. 4.2 ESD and Transients
    3. 4.3 Distance and Node Limitations
  7. 5LIN Transceiver Special Functions
    1. 5.1 Low-Power Modes
      1. 5.1.1 Sleep Mode
      2. 5.1.2 Standby Mode
    2. 5.2 Wakeup
      1. 5.2.1 Pin Wakeup
      2. 5.2.2 LIN Wakeup
      3. 5.2.3 Dominant Timeout
  8. 6Advantages and Disadvantages
  9. 7Conclusion
  10. 8Revision History

3.4 Bit-Rate Tolerance and Timing Requirements

The bit rate for LIN ranges from 1 to 20 kilobits per second, with a bit rate tolerance ±14%. This 14% value comes from the fact that low-cost, on-chip oscillators are used and with internal calibration, better than ±14% can be achieved. This accuracy allows detection of a break in the message stream, and with timing calibration using the synch field, the reception and transmission of messages are ensured by the message frames themselves. Temperature changes and voltage drift can cause changes in the bit rate, and the on-chip oscillator accounts for these variations when measuring the bit rate and generating the rest of the message frame (after the synch field).