SLLA662 March   2025 MCF8315A , MCF8315C , MCF8315C-Q1 , MCF8315D , MCF8316A , MCF8316C-Q1 , MCF8316D , MCF8329A , MCT8315A , MCT8316A , MCT8329A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2I2C Related Details for MCx83xx Family
    1. 2.1 TARGET_ID
    2. 2.2 CRC_EN
      1. 2.2.1 CRC Computational Details
    3. 2.3 MEM_SEC, MEM_PAGE, and MEM_ADDR
  6. 3I2C Secondary Device Feature Supported by MCx83xx Family
    1. 3.1 Clock Stretching
  7. 4Primary Device Read and Write Expected Flow
    1. 4.1 Read Sequence
    2. 4.2 Write Sequence
  8. 5Summary
  9. 6References

4.2 Write Sequence

Upon primary device write command, set the primary device to Tx mode. Prepare the data to be transmitted along with CRC bit if enabled. Set the TARGET_ID and set R/W bit as 1b before generating START condition. Transmit the control words and then the data byte by byte till all bytes are sent out and generate stop condition. If NACK received, retry sending data few times (recommended 5 retries). If still NACK received, generate STOP condition.

Note: Make sure at least 100us delay between each byte of data for reliable communication.
Primary Device I2C Write Expected Figure 4-2 Primary Device I2C Write Expected