SLLA662 March   2025 MCF8315A , MCF8315C , MCF8315C-Q1 , MCF8315D , MCF8316A , MCF8316C-Q1 , MCF8316D , MCF8329A , MCT8315A , MCT8316A , MCT8329A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2I2C Related Details for MCx83xx Family
    1. 2.1 TARGET_ID
    2. 2.2 CRC_EN
      1. 2.2.1 CRC Computational Details
    3. 2.3 MEM_SEC, MEM_PAGE, and MEM_ADDR
  6. 3I2C Secondary Device Feature Supported by MCx83xx Family
    1. 3.1 Clock Stretching
  7. 4Primary Device Read and Write Expected Flow
    1. 4.1 Read Sequence
    2. 4.2 Write Sequence
  8. 5Summary
  9. 6References

2.2 CRC_EN

If CRC_EN = 1, cyclic redundancy check (CRC) gets enabled otherwise CRC is disabled.

  1. In write operation
    Primary device is expected to send the CRC byte computed on the data and MCx83xx is expected to use the CRC byte to check the correctness of data received. The data to be included in CRC computation is as follows:
    1. Target ID + write bit.
    2. Control word – 3 bytes
    3. Data bytes – 2/4/8 bytes
  2. In read operation
    MCx83xx send CRC byte at the end of data bytes. The primary device is expected compute CRC to check for correctness of data sent by MCx83xx by comparing computed CRC against received CRC byte. The data to be included in CRC computation is as follows:
    1. Target ID + write bit
    2. Control word – 3 bytes
    3. Target ID + read bit
    4. Data bytes – 2/4/8 bytes
Note: EEPROM parity does not affect the I2C CRC computation. I2C CRC is computed strictly on the bytes specified above.