SLLA662 March   2025 MCF8315A , MCF8315C , MCF8315C-Q1 , MCF8315D , MCF8316A , MCF8316C-Q1 , MCF8316D , MCF8329A , MCT8315A , MCT8316A , MCT8329A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2I2C Related Details for MCx83xx Family
    1. 2.1 TARGET_ID
    2. 2.2 CRC_EN
      1. 2.2.1 CRC Computational Details
    3. 2.3 MEM_SEC, MEM_PAGE, and MEM_ADDR
  6. 3I2C Secondary Device Feature Supported by MCx83xx Family
    1. 3.1 Clock Stretching
  7. 4Primary Device Read and Write Expected Flow
    1. 4.1 Read Sequence
    2. 4.2 Write Sequence
  8. 5Summary
  9. 6References

4.1 Read Sequence

Upon primary device read command, first configure the primary device with the TARGET_ID and R/W bit as write. Configure the primary device in Tx mode. Prepare the control words to be sent to the secondary device. Generate I2C START condition and send the control words along with TARGET_ID and R/W bit set as 0. If NACK received, retry sending data few times (recommended 5 retries). If still NACK received, generate STOP condition.

Note: Make sure at least 100us delay between each byte of data for reliable communication

After writes are completed, configure the primary device to be in Rx mode. Once all data bytes and CRC packet (if enabled in control words) is received, send I2C STOP condition to complete the transaction.

Primary Device I2C Read Expected Figure 4-1 Primary Device I2C Read Expected