SLLA662 March   2025 MCF8315A , MCF8315C , MCF8315C-Q1 , MCF8315D , MCF8316A , MCF8316C-Q1 , MCF8316D , MCF8329A , MCT8315A , MCT8316A , MCT8329A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2I2C Related Details for MCx83xx Family
    1. 2.1 TARGET_ID
    2. 2.2 CRC_EN
      1. 2.2.1 CRC Computational Details
    3. 2.3 MEM_SEC, MEM_PAGE, and MEM_ADDR
  6. 3I2C Secondary Device Feature Supported by MCx83xx Family
    1. 3.1 Clock Stretching
  7. 4Primary Device Read and Write Expected Flow
    1. 4.1 Read Sequence
    2. 4.2 Write Sequence
  8. 5Summary
  9. 6References

2 I2C Related Details for MCx83xx Family

The data word format which the MCx83xx family follows for the I2C communication across all devices is shown in Table 2-1.

Table 2-1 I2C Data Word Format
TARGET_ID R/W CONTROL_WORD DATA CRC-8
A6 – A0 W0 CW23 - CW0 D15/D31/D63 - D0 C7 – C0
Table 2-2 I2C Control Word Format
OP_R/W CRC_EN DLEN MEM_SEC MEM_PAGE MEM_ADDR
CW23 CW22 CW21 – CW20 CW19 – CW16 CW15 – CW12 CW11 – CW0

Table 2-1 shows that the format consists of 7-bit TARGET_ID, followed by a read write bit (R/W bit). After this packet we send a 24-bit control word followed by (16/32/64 bit) DATA, and 8-bit CRC if CRC_EN is set in CONTROL_WORD. The data length can be configured within the CONTROL_WORD.

Detailed description for all fields can be found in the MCx83xx device data sheet under EEPROM access and I2C interface section. This section provides some key things to note regarding the usage of these fields.