SLLSF09F December   2017  – August 2026 ISO1042

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Transient Immunity
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Ratings
    7. 5.7  Insulation Specifications
    8. 5.8  Safety-Related Certifications
    9. 5.9  Safety Limiting Values
    10. 5.10 Electrical Characteristics - DC Specification
    11. 5.11 Switching Characteristics
    12. 5.12 Insulation Characteristics Curves
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CAN Bus States
      2. 7.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
      3. 7.3.3 Protection Features
        1. 7.3.3.1 TXD Dominant Timeout (DTO)
        2. 7.3.3.2 Thermal Shutdown (TSD)
        3. 7.3.3.3 Undervoltage Lockout and Default State
        4. 7.3.3.4 Floating Pins
        5. 7.3.3.5 Unpowered Device
        6. 7.3.3.6 CAN Bus Short Circuit Current Limiting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Bus Loading, Length and Number of Nodes
        2. 8.2.2.2 CAN Termination
      3. 8.2.3 Application Curve
        1. 8.2.3.1 Insulation Lifetime
    3. 8.3 DeviceNet Application
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 PCB Material
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Insulation Specifications

PARAMETERTEST CONDITIONSSPECIFICATIONSUNIT
DW-16DWV-8
IEC 60664-1
CLRExternal clearance(1)Side 1 to side 2 distance through air>8.15>8.5mm
CPGExternal Creepage(1)Side 1 to side 2 distance across package surface>8.15>8.5mm
DTIDistance through the insulationMinimum internal gap (internal clearance)>17>17µm
CTIComparative tracking indexIEC 60112; UL 746A>600>600V
Material GroupAccording to IEC 60664-1II
Overvoltage categoryRated mains voltage ≤ 600VRMSI-IVI-IV
Rated mains voltage ≤ 1000VRMSI-IIII-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)15001500VPK
VIOWMMaximum isolation working voltageAC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test;10601060VRMS
DC voltage21212121VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM, t = 60s (qualification); VTEST = 1.2 × VIOTM, t = 1s (100% production)70717071VPK
VIOSMMaximum surge isolation voltage
ISO1042(3)		Test method per IEC 62368-1, 1.2/50µs waveform1000010000VPK
Maximum surge isolation voltage
ISO1042B(3)		Test method per IEC 62368-1, 1.2/50µs waveform60006000VPK
qpdApparent charge(4)Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM, tm = 10s≤ 5≤ 5pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s;
ISO1042: Vpd(m) = 1.6 × VIORM, tm = 10s
ISO1042B: Vpd(m) = 1.2 × VIORM, tm = 10s		≤ 5≤ 5
At routine test (100% production),

Method b1: Vini = 1.2 × VIOTM, tini = 1s;


ISO1042: Vpd(m) = 1.875 × VIORM, tm = 1s
ISO1042B: Vpd(m) = 1.5 × VIORM, tm = 1s, or

Method b2: Vpd(m) = Vini, tm = tini

≤ 5≤ 5
CIOBarrier capacitance, input to output(5)VIO = 0.4 × sin (2 πft), f = 1MHz11pF
RIOInsulation resistance, input to output(5)VIO = 500V,  TA = 25°C> 1012> 1012Ω
VIO = 500V,  100°C ≤ TA ≤ 150°C> 1011> 1011
VIO = 500V at  TS = 150°C> 109> 109
Pollution degree22
Climatic category40/125/
21		40/125/
21
UL 1577
VISOWithstand isolation voltageVTEST = VISO , t = 60s (qualification); VTEST = 1.2 × VISO, t = 1s (100% production)50005000VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) ISO1042 is designed for safe electrical insulation and ISO1042B is designed for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of designed protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.