The ISOW644x device device has built-in UVLO on the V_DD and V_DDL supplies with positive-going and negative-going thresholds and hysteresis. The power converter supply (V_DD) needs to be above UVLO for the power converter to work. Logic supply (V_DDL) needs to be above UVLO for the signal path to work.

When the V_DD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits primary peak currents drawn from the V_DD supply and charges the V_ISO output in a controlled manner, avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the V_DD voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the secondary side V_ISO pin, the feedback data channel starts providing feedback to the primary controller. The regulation loop takes over and the isolated data channels go to the normal state defined by the respective input channels or the default states. Design must consider a sufficient time margin (typically 10ms with 10µF load capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.

When V_DD power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached. The V_ISO capacitor then discharges depending on the external load. The isolated data outputs on the V_ISO side are returned to the default state for the brief time that the V_ISO voltage takes to discharge to zero.